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參數(shù)資料
| 型號(hào)： | IS41C16257-60TI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE |
| 中文描述： | 256K X 16 FAST PAGE DRAM, 60 ns, PDSO40 |
| 封裝： | 0.400 INCH, TSOP2-44/40 |
| 文件頁(yè)數(shù)： | 4/17頁(yè) |
| 文件大?。?/td> | 160K |
| 代理商： | IS41C16257-60TI |
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IS41C16257
IS41LV16257
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
DR004-1B
05/24/99
ISSI
FUNCTIONAL DESCRIPTION
The IS41C16257 and the IS41LV16257 are CMOS DRAMs
optimized for high-speed bandwidth, low-power applications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 18 address bits. These are entered
nine bits (A0-A8) at a time. The row address is latched by
the Row Address Strobe (
RAS
). The column address is
latched by the Column Address Strobe (
CAS
).
RAS
is used
to latch the first nine bits and
CAS
is used to latch the latter
nine bits.
The IS41C16257 and the IS41LV16257 has two
CAS
controls,
LCAS
and
UCAS
. The
LCAS
and
UCAS
inputs
internally generate a
CAS
signal functioning in an identical
manner to the single
CAS
input on the other 256K x 16
DRAMs. The key difference is that each
CAS
controls its
corresponding I/O tristate logic (in conjunction with
OE
and
WE
and
RAS
).
LCAS
controls I/O0 - I/O7 and
UCAS
controls I/O8 - I/O15.
The IS41C16257 and the IS41LV16257
CAS
function is
determined by the first
CAS
(
LCAS
or
UCAS
) transitioning
LOW and the last transitioning back HIGH. The two
CAS
controls give the IS41C16257 both BYTE READ and BYTE
WRITE cycle capabilities.
Memory Cycle
A memory cycle is initiated by bringing
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensure proper device operation and data integrity any
memory cycle, once initiated, must not be ended or aborted
before the minimum t
RAS
time has expired. A new cycle
must not be initiated until the minimum precharge time t
RP
,
t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE
,
whichever occurs last, while holding
WE
HIGH. The column
address must be held for a minimum time specified by t
AR
.
Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OEA
are all satisfied. As a result, the access time is dependent
on the timing relationships between these parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE
,
whichever occurs last. The input data must be valid at or
before the falling edge of
CAS
or
WE
, whichever occurs last.
Refresh Cycle
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory:
1. By clocking each of the 512 row addresses (A0 through
A8) with
RAS
at least once every 8 ms. Any read, write,
read-modify-write or
RAS
-only cycle refreshes the ad-
dressed row.
2. Using a
CAS
-before-
RAS
refresh cycle.
CAS
-before-
RAS
refresh is activated by the falling edge of
RAS
, while
holding
CAS
LOW. In
CAS
-before-
RAS
refresh cycle, an
internal 9-bit counter provides the row addresses and the
external address inputs are ignored.
CAS
-before-
RAS
is a refresh-only mode and no data access
or device selection is allowed. Thus, the output remains in
the High-Z state during the cycle.
Power-On
After application of the V
CC
supply, an initial pause of
200
μ
s is required followed by a minimum of eight initialization
cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with V
CC
or be held at a valid V
IH
to avoid current surges.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS41LV16257-35K | 256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE |
| IS41LV16257-35KI | 256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE |
| IS41LV16257-35T | 256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE |
| IS41LV16257-35TI | 256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE |
| IS41LV16257-60K | 256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS41C16257A-35KI | 制造商:Integrated Silicon Solution Inc 功能描述:256K X 16 FAST PAGE DRAM, 35 ns, PDSO40 |
| IS41C16257C | 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:4Mb DRAM WITH FAST PAGE MODE |
| IS41C16257C-35TLI | 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 4M 5V FastPageMode 35ns, 40 pin TSOP II RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問(wèn)時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS41C16257C-35TLI-TR | 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 4M,5V,Fast Page Mode 動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器,Async,35ns RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問(wèn)時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS41C1664-30T | 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:64K x 16 bit Dynamic RAM with EDO Page Mode |
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