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參數(shù)資料
型號(hào)： IRS20124STRPBF
廠(chǎng)商： International Rectifier
文件頁(yè)數(shù)： 12/27頁(yè)
文件大?。?/td> 0K
描述： IC DRIVER DGTL AUDIO 14-SOIC
標(biāo)準(zhǔn)包裝： 2,500
類(lèi)型： MOSFET 驅(qū)動(dòng)器
應(yīng)用： 放大器，接收器
安裝類(lèi)型： 表面貼裝
封裝/外殼： 14-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 14-SOIC（窄型）
包裝： 帶卷 (TR)
www.irf.com
2
IRS20124S(PbF)
Symbol
Definition
Min.
Max.
Units
VB
High-side floating supply voltage
-0.3
220
Vs
High-side floating supply voltage
VB-20
VB+0.3
VHO
High-side floating output voltage
Vs-0.3
VB+0.3
VCC
Low-side fixed supply voltage
-0.3
20
VLO
Low-side output voltage
-0.3
Vcc+0.3
VIN
Input voltage
-0.3
Vcc+0.3
VOC
OC pin input voltage
-0.3
Vcc+0.3
VOCSET1
OCSET1 pin input voltage
-0.3
Vcc+0.3
VOCSET2
OCSET2 pin input voltage
-0.3
Vcc+0.3
dVs/dt
Allowable Vs voltage slew rate
-
50
V/ns
PD
Maximum power dissipation
-
1.25
W
RthJA
Thermal resistance, junction to ambient
-
100
°C/W
TJ
Junction temperature
-
150
TS
Storage temperature
-55
150
TL
Lead temperature (soldering, 10 seconds)
-
300
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters
are absolute voltages referenced to COM. All currents are defined positive into any lead. The thermal resistance and power
dissipation ratings are measured under board mounted and still air conditions.
Description
The IRS20124 is a high voltage, high speed power MOSFET driver with internal deadtime and shutdown
functions specially designed for Class D audio amplifier applications.
The internal dead time generation block provides accurate gate switch timing and enables tight deadtime
settings for better THD performances.
In order to maximize other audio performance characteristics, all switching times are designed for immunity
from external disturbances such as VCC perturbation and incoming switching noise on the DT pin. Logic
inputs are compatible with LSTTL output or standard CMOS down to 3.0 V without speed degradation. The
output drivers feature high current buffers capable of sourcing 1.0 A and sinking 1.2 A. Internal delays are
optimized to achieve minimal deadtime variations. Proprietary HVIC and latch immune CMOS technologies
guarantee operation down to Vs= –4 V, providing outstanding capabilities of latch and surge immunities with
rugged monolithic construction.
V
°C
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