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參數(shù)資料
| 型號： | IRMCS2033 |
| 廠商： | International Rectifier |
| 英文描述： | Low Voltage Sensorless Drive Design Platform for Permanent Magnet Motors |
| 中文描述： | 低電壓驅動設計平臺傳感器的永磁電動機 |
| 文件頁數(shù)： | 18/21頁 |
| 文件大?。?/td> | 424K |
| 代理商： | IRMCS2033 |
IRMCS2033
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
17
Address Byte
HP_A = 1
Data Byte 0
HP_A = 0
…………….
HP_A = 0
Data Byte N
HP_A = 0
Host Parallel Data Transfer Format
Figure 9 and Table 2 show read cycle timing for the host parallel interface. Figure 10 and Table 3 show write cycle
timing.
HP_nWE
HP_D [7:0]
HP_nOE
HP_A
HP_nCS
t
HPCSN
VALID
t
HPWENS
t
HPAS
t
HPDZ
t
HPOEN
t
AHPD
t
HPOENS
t
HPA
t
HPZD
Figure 9. Host Parallel Read Cycle Timing
SYMBOL
DESCRIPTION
MIN
MAX
UNIT
S
ns
ns
ns
ns
ns
ns
ns
ns
NOTE
t
HPCSN
t
HPWENS
t
HPAS
t
AHPD
t
HPZD
t
HPDZ
t
HPOENS
t
HPOEN
HP_nCS Period
HP_nWE Setup
HP_A Setup
HP_D [7:0] Access
HP_D [7:0] Active
HP_D [7:0] High Impedance
HP_nOE Setup
HP_nOE Period
70
40
40
60
0
0
40
70
Note 3
Note 3
105
9
6
Table 2: Host Parallel Read Cycle Timing
Note:
1. HP_nOE, HP_nWE must be stable before the high to low transition of HP_nCS.
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