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參數(shù)資料
| 型號： | IRMCS2033 |
| 廠商： | International Rectifier |
| 英文描述： | Low Voltage Sensorless Drive Design Platform for Permanent Magnet Motors |
| 中文描述： | 低電壓驅(qū)動設(shè)計平臺傳感器的永磁電動機 |
| 文件頁數(shù)： | 17/21頁 |
| 文件大?。?/td> | 424K |
| 代理商： | IRMCS2033 |
IRMCS2033
Parallel Interface Port
IRMCS2033 provides an 8-bit parallel interface port to facilitate microprocessor interface. The interface is generic and
compatible with most common 8-bit parallel interfaces such as MCS8051, some Motorola 8-bit uP, Microchip, etc.
Figure 8 shows the connection diagram. The connector, J5, is a 2-by-10 header connector.
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
16
J5
HEADER 20
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VCC
HP_D0
HP_D1
HP_D2
HP_D3
HP_D4
HP_D5
HP_D6
HP_D7
NA
NA
NA
NA
HP_nCS
HP_nWE
HP_nOE
HP_A
Figure 8. Parallel Interface Port
Each signal is 3.3V level and the data bus is multiplexed. Table 1 summarizes each signal definition.
Signal
I/O
1
Description
HP_nCS
I
Active low Host Port Chip Select
HP_nOE
I
Active Low Host Port Output Enable
HP_nWE
I
Active low Host Port Write Enable
HP_A
I
Host Port Register Address. 1 = Address register, 0 = Data Register
HP_D
n
I/O
Bidirectional Host Port data bus, where
n
= data bit 0 - 7
Table 1. Microprocessor Interface Module Signal Definitions
The IRMCK203 contains an address register that is updated with the Host Register address when HP_A = 1. After
each subsequent data byte is either read or written, the internal address register is incremented. The diagram below
shows that Data Bytes 0 to N would access register locations initially specified by the Address Byte. The Address
Byte with the HP_A signal can be asserted at any time.
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