![](http://datasheet.mmic.net.cn/30000/MR80C32-20-D_datasheet_2377239/MR80C32-20-D_83.png)
83
8154B–AVR–07/09
ATmega16A
Note:
1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.
However, the functionality and location of these bits are compatible with previous versions of
the timer.
Bit 5:4 – COM01:0: Compare Match Output Mode
These bits control the Output Compare pin (OC0) behavior. If one or both of the COM01:0 bits
are set, the OC0 output overrides the normal port functionality of the I/O pin it is connected to.
However, note that the Data Direction Register (DDR) bit corresponding to the OC0 pin must be
set in order to enable the output driver.
When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0
bit setting.
Table 14-3 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a
normal or CTC mode (non-PWM).
Table 14-4 shows the COM01:0 bit functionality when the WGM01:0 bits are set to fast PWM
mode.
Note:
1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare
more details.
Table 14-5 shows the COM01:0 bit functionality when the WGM01:0 bits are set to phase cor-
rect PWM mode.
Table 14-2.
Waveform Generation Mode Bit Description
(1)Mode
WGM01
(CTC0)
WGM00
(PWM0)
Timer/Counter Mode of
Operation
TOP
Update of
OCR0
TOV0 Flag
Set-on
0
Normal
0xFF
Immediate
MAX
1
0
1
PWM, Phase Correct
0xFF
TOP
BOTTOM
2
1
0
CTC
OCR0
Immediate
MAX
3
1
Fast PWM
0xFF
BOTTOM
MAX
Table 14-3.
Compare Output Mode, non-PWM Mode
COM01
COM00
Description
0
Normal port operation, OC0 disconnected.
0
1
Toggle OC0 on compare match
1
0
Clear OC0 on compare match
1
Set OC0 on compare match
Table 14-4.
Compare Output Mode, Fast PWM M
odeCOM01
COM00
Description
0
Normal port operation, OC0 disconnected.
01
Reserved
1
0
Clear OC0 on compare match, set OC0 at BOTTOM,
(non-inverting mode)
1
Set OC0 on compare match, clear OC0 at BOTTOM,
(inverting mode)