![](http://datasheet.mmic.net.cn/30000/MR80C32-20-D_datasheet_2377239/MR80C32-20-D_244.png)
244
8154B–AVR–07/09
ATmega16A
In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when
enabling the ADC. The user is advised to wait at least 200 ns after enabling the ADC before
controlling/observing any ADC signal, or perform a dummy conversion before using the first
result.
The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal
low (Sample mode).
As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3 when
the power supply is 5.0V and AREF is externally connected to V
CC.
The recommended values from
Table 24-6 are used unless other values are given in the algo-
rithm in
Table 24-7. Only the DAC and Port Pin values of the Scan-chain are shown. The column
“Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register
with the succeeding columns. The verification should be done on the data scanned out when
scanning in the data on the same row in the table.
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-
quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at
least five times the number of scan bits divided by the maximum hold time, t
hold,max.
Table 24-7.
Algorithm for Using the ADC
Step
Actions
ADCEN
DAC
MUXEN
HOLD
PRECH
PA3.
Data
PA3.
Control
PA3.
Pullup_
Enable
1
SAMPLE_
PRELOAD
1
0x200
0x08
1
0
2
EXTEST
1
0x200
0x08
0
1
0
3
1
0x200
0x08
1
0
4
1
0x123
0x08
1
0
5
1
0x123
0x08
1
0
6
Verify the
COMP bit
scanned
out to be 0
1
0x200
0x08
1
0
7
1
0x200
0x08
0
1
0
8
1
0x200
0x08
1
0
9
1
0x143
0x08
1
0
10
1
0x143
0x08
1
0
11
Verify the
COMP bit
scanned
out to be 1
1
0x200
0x08
1
0
The lower limit is:
1024 1,5
V 0,95 5V
291
0x123
==
The upper limit is:
1024 1,5
V 1,05 5V
323
0x143
==