參數(shù)資料
型號： IR80C52CXXX-12:RD
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44
文件頁數(shù)： 27/101頁
文件大?。?/td> 3398K
54
Figure 5-10. Exemplary Timing of an RX_AACK Transaction for Slotted Operation
5.2.3.6 Timing
A general timing example of an RX_AACK transaction is shown in Figure 5-11. In this
example, a data frame with an ACK request is received. The AT86RF212 changes to
state BUSY_RX_AACK after SFD detection. The completion of the frame reception is
indicated by a TRX_END interrupt. The interrupts IRQ_2 (TX_START) and IRQ_5 (AMI)
are disabled in this example. The ACK frame is automatically transmitted after
aTurnaroundTime (12 symbols), assuming default acknowledgment frame start timing.
The interrupt latency t9 is specified in section 10.4.
Figure 5-11. Exemplary Timing of an RX_AACK Transaction
RX_AACK_ON
BUSY_RX_AACK
State
Frame Type
RX_AACK_ON
RX/TX
RX
TX
TRX_END
IRQ
RX
tIRQ
Data Frame (ACK=1)
ACK Frame (Frame Pending = 0)
SFD
...
SUCCESS_WAIT_FOR_ACK
SUCCESS
TRAC_STATUS
aTurnaroundTime
(AACK_ACK_TIME)
Time
5.2.4 TX_ARET_ON – Transmit with Automatic Retry and CSMA-CA Retry
Overview
The TX_ARET Extended Operating Mode supports the frame transmission process as
defined by IEEE 802.15.4-2006. It is invoked as described in section 5.2.1 by writing
TX_ARET_ON to register subfield TRX_CMD (register 0x02, TRX_STATE).
AT86RF212
8168C-MCU Wireless-02/10
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