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參數(shù)資料
| 型號： | IR3Y48M |
| 廠商： | Sharp Corporation |
| 英文描述： | CCD Signal Process & Digital Interface IC |
| 中文描述： | CCD信號處理 |
| 文件頁數(shù)： | 14/31頁 |
| 文件大?。?/td> | 176K |
| 代理商： | IR3Y48M |
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14
IR3Y48M
Serial Interface Circuit
The internal registers of IR3Y48M are controlled
through 3-wire serial interface.
The 16-bit length control data consists of 2-bit
operation code, 4-bit address, and 10-bit data. The
controller should set each bit synchronizing to SCK
falling since IR3Y48M (receiver) acquire data at
SCK rising edge. The data is valid while CSN is
low.
The written data comes effective at rising edge of
CSN.
Fix CSN to high when no access is conducted.
It is forbidden to write data to the address that is
not listed.
Always give 16 times SCK rising during CSN low.
All data are ignored when SCK rising during CSN
low is less than 16.
The effect of operation code is determined by OP
pin control.
When OP pin is high, the data are always valid
regardless of O
0
and O
1
.
When OP pin is low, operation code control is
active, and the data is written only when both O
0
=
0 and O
1
= 1 are true.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CSN
SCK
SDATA
Ope
Code
Address
Data
O
0
O
1
A
0
A
1
A
2
A
3
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
Serial Write Control
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