參數(shù)資料
型號: IR3629A
廠商: International Rectifier
英文描述: HIGH FREQUENCY SYNCHRONOUS PWM BUCK CONTROLLER WITH POWER GOOD OUTPUT
中文描述: 高頻同步PWM降壓控制器與電源良好輸出
文件頁數(shù): 6/23頁
文件大小: 598K
代理商: IR3629A
IR3629/IR3629A MPbF
11/26/2007
Feedback Compensation
The IR3629 is a voltage mode controller. The
control loop is a single voltage feedback path
including error amplifier and error comparator. To
achieve fast transient response and accurate
output regulation, a compensation circuit is
necessary. The goal of the compensation
network is to provide a closed-loop transfer
function with the highest 0dB crossing frequency
and adequate phase margin (greater than 45o).
The output LC filter introduces a double pole, –
40dB/decade gain slope above its corner
resonant frequency, and a total phase lag of 180o
(see figure 13). The resonant frequency of the LC
filter is expressed as follows:
Figure 13 shows gain and phase of the LC filter.
Since we already have 180o phase shift from the
output filter a lone , the system risks being
unstable.
The IR3629/29A’s error amplifier is a differential-
input transconductance amplifier. The output is
available for DC gain control or AC phase
compensation.
The error amplifier can be compensated either in
type II or type III compensation. When it is used
in type II compensation the transconductance
properties of the error amplifier become evident
and can be used to cancel one of the output filter
poles. This will be accomplished with a series RC
circuit from Comp pin to ground as shown in
figure 14.
This method requires the output capacitor should
have
enough
ESR
to
satisfy
stability
requirements. In general the output capacitor’s
ESR generates a zero typically at 5kHz to 50kHz
which is essential for an acceptable phase
margin.
(11)
-
C
L
2
1
F
o
LC
=
π
Gain
FLC
0dB
Phase
0
FLC
-180
Frequency
-40dB/decade
Fig. 13: Gain and Phase of LC filter
The ESR zero of the output capacitor expressed
as follows:
The transfer function (Ve/Vo) is given by:
The (s) indicates that the transfer function varies
as a function of frequency. This configuration
introduces a gain and zero, expressed by:
The gain is determined by the voltage divider and
error amplifier’s transconductance gain.
First select the desired zero-crossover frequency
(Fo):
Use the following equation to calculate R3:
Where:
V
in = Maximum Input Voltage
V
osc = Oscillator Ramp Voltage
F
o = Crossover Frequency
F
ESR = Zero Frequency of the Output Capacitor
F
LC = Resonant Frequency of the Output Filter
R
8 and R9 = Feedback Resistor Dividers
g
m = Error Amplifier Transconductance
1.28 = Empirical number to compensate thermal,
process variations and components tolerances
(12)
-
C
ESR
2
1
F
o
ESR
*
π
=
Fig. 14: TypeII compensation network
and its asymptotic gain plot
(13)
-
sC
C
sR
1
R
g
s
H
4
3
8
9
m
+
+
=
*
)
(
()
[]
(15)
-
C
R
2
1
F
(14)
-
R
*
R
g
s
H
4
3
z
3
8
9
m
*
π
=
+
=
(
)
s
o
ESR
o
F
1/10
~
1/5
F
and
F
*
>
(15A)
-
*
.
*
)
(
*
m
LC
in
ESR
o
osc
g
R
F
V
R
F
V
R
9
2
9
8
3
28
1
+
=
Ve
VOUT
VREF
R9
R8
R3
C4
E/A
FZ
H(s) dB
Frequency
Gain(dB)
Fb
Comp
CPOLE
14
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