參數(shù)資料
型號: IR3500MTRPBF
廠商: International Rectifier
英文描述: XPHASE3TM VR11.0 & AMD PVID CONTROL IC
中文描述: XPHASE3TM VR11.0
文件頁數(shù): 30/47頁
文件大小: 778K
代理商: IR3500MTRPBF
IR3500
Page 30 of 47
June 12, 2007
DESIGN PROCEDURE
Oscillator Resistor
Rosc
The oscillator of IR500 generates square-wave pulses to synchronize the phase ICs. The switching frequency of
each phase converter equals the PHSOUT frequency, which is set by the external resistor R
OSC
according to
the
curve in Figure 23. The CLKOUT frequency equals the switching frequency multiplied by the phase number. The
Rosc sets the reference current used for the no load offset and OCSET which is given by Figure 23 and equals:
595
.
=
=
Rosc
IOCSET
ISETPT
(1)
Soft Start Capacitor
C
SS/DEL
The soft start capacitor C
SS/DEL
programs five different time parameters. They include soft start delay time, soft
start time, VID sample delay time, VR ready delay time and over-current fault latch delay time after VR ready.
For the converter using VR11 VID with boot voltage, the SS/DEL pin voltage controls the slew rate of the
converter output voltage, as shown in Figure 10. After the ENABLE pin voltage rises above 0.85V, there is a soft-
start delay time TD1
,
after which the error amplifier output is released to allow the soft start of output voltage. The
soft start time TD2 represents the time during which converter voltage rises from zero to 1.1V
.
The
VID sample
delay time (TD3) is the time period when VID stays at boot voltage of 1.1V. VID rise or fall time (TD4) is the time
when VID changes from boot voltage to the final voltage. The VR ready delay time (TD5) is the time period from
VR reaching the final voltage to the VR ready signal being issued, which is determined by the delay comparator
threshold.
C
SS/DEL
= 0.1uF meets all the specifications of TD1 to TD5, which are determined by (2) to (6) respectively.
4
*
4
*
1
=
=
CHG
I
1
*
1
*
2
=
=
CHG
I
)
4
3
*
3
=
I
6
/
/
10
*
5
52
DEL
SS
DEL
SS
C
C
TD
(2)
6
/
/
10
*
5
52
DEL
SS
DEL
SS
C
C
TD
(3)
6
/
/
10
*
5
52
7
*
=
DEL
SS
CHG
DEL
SS
C
C
TD
(4)
6
/
/
10
*
5
52
1
*
1
*
4
=
=
DAC
DEL
SS
CHG
DAC
DEL
SS
V
C
I
V
C
TD
(5)
4
10
*
5
52
92
.
*
4
)
92
.
*
5
6
/
/
TD
C
TD
I
C
TD
DEL
SS
CHG
DEL
SS
=
=
(6)
For the converter using VR 11 VID without boot voltage or AMD 5-bit and 6-bit VIDs, the SS/DEL pin voltage
controls the slew rate of the converter output voltage, as shown in Figure 11. After the ENABLE pin voltage rises
above 0.85V/1.2V, there is a soft-start delay time TD1
,
after which the error amplifier output is released to allow
the soft start. The soft start time TD2 represents the time during which converter voltage rises from zero to Vo
.
VR
ready delay time (TD3) is the time period from VR reaching the final voltage to the VR ready signal being issued.
Calculate C
SS/DEL
based on the required soft start time (TD2).
O
O
CHG
DEL
SS
V
TD
V
I
TD
C
6
/
10
*
5
52
*
2
*
2
=
=
(7)
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