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| 型號： | IR22771STRPBF |
| 廠商： | International Rectifier |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 441K |
| 描述： | IC CURRENT SENSE 16SOIC |
| 標準包裝： | 500 |
| 功能： | 電流感應 |
| 輸入電壓： | 8 V ~ 20 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
IR22771S/IR21771S(PbF)
15
www.irf.com
c) Bootstrap Capacitor
For high T
HON
designs where is used an electrolytic
tank capacitor, its ESR must be considered. This
parasitic resistance develops a voltage divider with
R
boot
generating a voltage step on V
BS
at the first
charge of bootstrap capacitor. The voltage step and
the related speed (dV
BS
/dt) should be limited. As a
general rule, ESR should meet the following
constraint:
V
V
R
ESR
ESR
CC
BOOT
3
d
?/DIV>
+
Parallel combination of small ceramic and large
electrolytic capacitors is normally the best
compromise, the first acting as fast charge thank for
the gate charge only and limiting the dV
BS
/dt by
reducing the equivalent resistance while the second
keeps the V
BS
voltage drop inside the desired V
BS
.
d) Bootstrap Diode
The diode must have a BV> 600V (or 1200V
depending on application) and a fast recovery time
(t
rr
< 100 ns) to minimize the amount of charge fed
back from the bootstrap capacitor to V
CC
supply.
3
PCB LAYOUT TIPS
3.1 Distance from H to L voltage
The IR22771S/IR21771S package (wide body)
maximizes the distance between floating (from DC-
to DC+) and low voltage pins (V
SS
). Its strongly
recommended to place components tied to floating
voltage in the respective high voltage portions of the
device (V
B
, V
S
) side.
3.2 Ground plane
Ground plane must NOT be placed under or nearby
the high voltage floating side to minimize noise
coupling.
Figure 17: antenna loops
3.3 Antenna loops and inputs
connection
Current loops behave like antennas able to receive
EM noise. In order to reduce EM coupling, loops
must be reduced as much as possible. Figure 17
shows the high side shunt loops.
Moreover it is strongly suggested to use Kelvin
connections for V
in+
and V
in-
to shunt paths and star-
connect V
S
to V
in-
close to the shunt resistor as
explained in Fig. 18.
Figure 18: Recommended shunt connection
3.4 Supply capacitors
The supply capacitors must be placed as close as
possible to the device pins (V
CC
and V
SS
for the
ground tied supply, V
B
and V
S
for the floating
supply) in order to minimize parasitic traces
inductance/resistance.
VS
VB
Vin-
Vin+
VS
VB
Vin-
Vin+
Antenna
Loop
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
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