參數(shù)資料
型號(hào)： IR1153STRPBF
廠商： International Rectifier
文件頁(yè)數(shù)： 9/20頁(yè)
文件大?。?/td> 380K
描述： IC PFC ONE CYCLE CONTROL 8SOIC
特色產(chǎn)品： International Rectifier - uPFC? Power Factor Correction Ics
標(biāo)準(zhǔn)包裝： 1
模式： 連續(xù)導(dǎo)電（CCM）
頻率 - 開(kāi)關(guān)： 22.2kHz
電流 - 啟動(dòng)： 26µA
電源電壓： 14 V ~ 17 V
工作溫度： -25°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOIC
包裝： 標(biāo)準(zhǔn)包裝
其它名稱(chēng)： IR1153STRPBFDKR
 
IR1153S
 
 
www.irf.com
9 
?2011 International Rectifier
 
IR1153 General Description
Programmable Soft Start
The soft start process controls the rate of rise of the
voltage feedback loop error signal thus providing a
linear increase of the RMS input current that the
PFC converter will admit. The soft start time is
essentially controlled by voltage error amplifier
compensation   components   selected   and   is
therefore user programmable to some degree
based on desired voltage feedback loop crossover
frequency.
 
Gate Drive Capability
The gate drive output stage of the IC is a totem
pole   driver   with   750mA   peak   current   drive
capability. The gate drive is internally clamped at
14.1V (Typ). Gate drive buffer circuits (especially
cost-effective base-followers) can be easily driven
with the GATE pin of the IC to suit any system
power level.
 
System Protection Features
IR1153   protection   features   include   Brown-out
protection (BOP), Open-loop protection (OLP),
Overvoltage protection (OVP), Cycle-by-cycle peak
current limit (IPK LIMIT), Soft-current limit and VCC
under voltage lock-out (UVLO).
 
- BOP is based on direct input line sensing using a
resistor divider/RC filter network. If BOP pin falls
below the Brown-out protection threshold V
BOP
, a
Brown-out situation is immediately detected the
following response is executed - the gate drive
pulse is disabled, VCOMP is actively discharged
and IC is pushed into Stand-by Mode. The IC re-
enters   normal   operation   only   after   BOP   pin
exceeds V
BOP(EN)
. During start-up the IC is held in
Stand-by Mode until this pin exceeds V
BOP(EN)
.
 
- OLP is activated whenever the VFB pin voltage
falls below V
OLP
  threshold. Once open loop is
detected the following response is immediately
executed - the gate drive is immediately disabled,
VCOMP is actively discharged and the IC is
pushed into Stand-by mode. There is no voltage
hysteresis associated with this feature. During
start-up the IC is held in Stand-by Mode until VFB
exceeds V
OLP
.
 
- The OVP pin is a dedicated pin for overvoltage
protection that safeguards the system even if
there is a break in the VFB feedback loop due to
resistor divider failure etc. An overvoltage fault is
triggered when OVP pin voltage exceeds the V
OVP
 
threshold of 106%VREF. The response of the IC
is to immediately terminate the gate drive output
and hold it in that state. The gate drive is re-
enabled only after OVP pin voltage drops below
V
OVP(RST)
  threshold of 103% VREF. The exact
voltage level at which overvoltage protection is
triggered can be programmed by the user by
carefully designing the OVP pin resistor divider. It
is recommended NOT to set the OVP voltage
trigger limit less than 106% of DC bus voltage,
since this can endanger the situation where the
OVP reset limit will be less than the DC bus
voltage regulation point  in this condition the
voltage loop can become unstable.
 
- Soft-current limit is an output voltage fold-back
type protection feature encountered when the
PFC converter input current exceeds to a point
where the V
m
  voltage saturates. As mentioned
earlier, the amplitude of input current is directly
proportional to V
m
, the error voltage of the
feedback loop. V
m
  is clamped to a certain
maximum   voltage   inside   the   IC   (given   by
V
COMP,EFF
  parameter in datasheet). If the input
current causes the V
m
 voltage to saturate at its
maximum value, then any further increase in input
current will cause the duty cycle to droop which
immediately forces the V
OUT
 voltage of the PFC
converter to fold-back. Since the highest current
is at the peak of the AC sinusoid, the droop in
duty cycle commences at the peak of the AC
sinusoid    when    the    soft-current    limit    is
encountered. In most converters, the design of
the current sense resistor is performed based on
soft-current limit (i.e. V
m
  saturation) and at the
system condition which demands highest input
current (minimum V
AC
 & maximum P
OUT
).
 
- Cycle-by-cycle peak current limit protection
instantaneously    turns-off    the    gate    output
whenever the ISNS pin voltage exceeds V
ISNS(PK)
 
threshold in magnitude. The gate drive is held in
the low state as long as the overcurrent condition
persists. The gate drive is re-enabled when the
magnitude of ISNS pin voltage falls below the
V
ISNS(PK)
   threshold.   This   protection   feature
incorporates a leading edge blanking circuit to
improve noise immunity.  
 
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