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參數(shù)資料
| 型號： | IR1153STRPBF |
| 廠商： | International Rectifier |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 380K |
| 描述： | IC PFC ONE CYCLE CONTROL 8SOIC |
| 特色產(chǎn)品： | International Rectifier - uPFC? Power Factor Correction Ics |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 模式： | 連續(xù)導(dǎo)電（CCM） |
| 頻率 - 開關(guān)： | 22.2kHz |
| 電流 - 啟動： | 26µA |
| 電源電壓： | 14 V ~ 17 V |
| 工作溫度： | -25°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | IR1153STRPBFDKR |
IR1153S
www.irf.com
11
?2011 International Rectifier
IR1153 Modes of operation
Referenced to States & Transition Diagram
UVLO/Sleep Mode: The IC is in the UVLO/Sleep
mode when VCC pin voltage is below V
CC,ON
at
start-up or when VCC pin voltage drops below
V
CC,UVLO
during normal operation or when OVP/EN
pin voltage is below V
SLEEP
. The UVLO/Sleep
mode is accessible from any other state of
operation. This mode can be actively invoked by
pulling the OVP/EN pin below V
SLEEP
even if VCC
pin voltage is above V
CC,ON
. In the UVLO/Sleep
state, the gate drive circuit is inactive, most of the
internal circuitry is unbiased and the IC draws a
quiescent current of I
SLEEP
which is less than
75uA. Also, the internal logic of the IC ensures
that whenever the Sleep mode is actively invoked,
the COMP pin is actively discharged below
V
COMP,START
threshold prior to entering the sleep
mode, in order to facilitate soft-start upon
resumption of operation.
Stand-by Mode: The IC is placed in Stand-by
mode whenever an Open-loop and/or a Brown-out
situation is detected. A Brown-out situation is
sensed when BOP pin voltage is less than
V
BOP(EN)
prior to system start-up and when BOP
pin voltage drops below V
BOP
after start-up. An
Open-loop situation is sensed anytime VFB pin
voltage is less than V
OLP
. All internal circuitry is
biased in the Stand-by Mode, but the gate is
inactive and the IC draws a few mA of current.
This state is accessible from any other state of
operation of the IC. COMP pin is actively
discharged to below V
COMP,START
whenever this
state is entered from normal operation in order to
facilitate soft-start upon resumption of operation.
Soft Start Mode: During system start-up, the soft-
start mode is activated once the VCC voltage has
exceeded V
CC,ON
, the VFB pin voltage has
exceeded V
OLP
and BOP pin voltage has
exceeded V
BOP(EN)
and VCOMP voltage is less
than V
COMP,START
i.e. a pre-bias on COMP pin
greater than V
COMP,START
threshold will not allow IC
to commence operation. The soft start time is the
time required for the VCOMP voltage to charge
through its entire dynamic range i.e. through
V
COMP,EFF
. As a result, the soft-start time is
dependent upon the component values selected
for compensation of the voltage loop on the
COMP pin. To an extent, keeping in mind the
voltage feedback loop considerations, the soft-
system start time is programmable.
As VCOMP voltage rises gradually, the IC allows
a higher and higher RMS current into the PFC
converter. This controlled increase of the input
current amplitude contributes to reducing system
component stress during start-up.
Normal Mode: The IC enters the normal
operating mode once the soft start transition has
been completed (for all practical purposes there is
essentially no difference between the soft-start
and normal modes). At this point the gate drive is
switching and all protection functions of the IC are
active. If, from the normal mode, the IC is pushed
into either a Stand-by mode or UVLO/Sleep mode
then COMP pin is actively discharged below
V
COMP,START
and system will go through soft-start
upon resumption of operation.
OVP Mode: The IC enters OVP mode whenever
an overvoltage condition is detected. A system
overvoltage condition is recognized when
OVP/EN pin voltage exceeds V
OVP
threshold.
When this happens the IC immediately disables
the gate drive and holds it in that state. The gate
drive is re-enabled only when OVP/EN pin
voltages are less than V
OVP(RST)
threshold. This
state is accessible from both the soft start and
normal modes of operation.
IPK LIMIT Mode: The IC enters IPK LIMIT mode
whenever the magnitude of ISNS pin voltage
exceeds the V
ISNS(PK)
threshold triggering cycle-by-
cycle peak overcurrent protection. When this
happens, the IC immediately disables the gate
drive and holds it in that state. Gate drive is re-
enabled when magnitude of ISNS pin voltage
drops below V
ISNS(PK)
threshold. This state is
accessible from both the soft start and normal
modes of operation.
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