參數(shù)資料
型號： IQX320-PB416
英文描述： User Programmable Special Function ASIC
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 27/65頁
文件大?。?/td> 620K
代理商： IQX320-PB416
IQX Family Data Sheet
June 2000
Revision 5.0
27
4.0 P
IN
S
UMMARY
IQX320
IQX240B
P000 - P193,
P225
IQX160
P000 - P103,
P107, P113,
P118, P119,
P123, P124,
P129, P130,
P135, P136
IQX128B
P000 - P083
DIR
I/O
Description
P000 - P259,
P262, P264, P266,
P274, P276, P278,
P280, P282, P284,
P286, P288, P290,
P292, P294, P305
Dedicated I/O Ports
P260, P261, P263,
P265, P267
P194, P195,
P196, P197,
P198
P104, P105,
P106, P108,
P109
P84 -P88
I/O
Shared I/O Ports
I/O Ports shared with General Tristate Control GT12 - GT8, used for Input Enable (IE) and
Output Enable (OE) Signals.
P268 - P272
P199 - P203
P110, P111,
P112, P114,
P115
P89 -P93
I/O
Shared I/O Ports
I/O Ports shared with General Clock Control GC12 - GC8, used for Clock (CLK) and Clock
Enable (CKE) Signals.
P273, P275, P277,
P279, P281
P204 - P208
P116, P117,
P120, P121,
P122
P125-P128,
P138, P137
P94 -P98
I/O
Shared I/O Ports
I/O Ports shared with Key Control K4 - K0, used for generating Clock (CLK), Clock Enable
(CKE), Input Enable (IE) and Output Enable (OE) signals.
P283, P285,
P287, P289
P209-P212
P99-P102,
P108, P107
I/O
Shared I/O Ports
I/O Ports shared with General Clock Control GC7-GC4 for IQX320 and IQX240B and GC7-
GC2 for remaining devices, used for Clock (CLK) and Clock Enable (CKE) Signals.
Shared I/O Ports
I/O Ports shared with General Tristate Control GT7 - GT5 for IQX320 and IQX240B and GT7
- GT4 for remaining devices, used for Input Enable (IE) and Output Enable (OE) Signals.
(Dedicated) General Tristate Control Pins
Used for Input Enable (IE) and Output Enable (OE) Signals.
(Dedicated) General Clock Control Pins
Used for Clock (CLK) and Clock Enable (CKE) signals.
Shared I/O Ports
I/O Ports shared with Column Address (CA) Bus
P291, P293, P295
P213 - P215
P131 - P134
P103 - P106
I/O
GT4 - GT0
GT4 - GT0
GT3 - GT0
GT3 - GT0
I
GC3 - GC0
GC3 - GC0
GC1 - GC0
GC1 - GC0
I
P296 - P304
CA0 - CA8
P216 - P224
CA0 - CA8
P140 - P147
CA0 - CA7
P110 - P116
CA0 - CA6
I/O
P306 - P314
RA0 - RA8
P226 - P234
RA0 - RA8
P148 - P155
RA0 - RA7
P117 - P123
RA0 - RA6
I/O
Shared I/O Ports
I/O Ports shared with Row Address (RA) Bus
P315 - P317
P235 - P237
P139, P156,
P157
P109, P124,
P125
I/O
Shared I/O Ports
I/O Ports shared with P/S, C0 AND C1
P318, P319
P238, P239
P158, P159
P126, P127
I/O
Shared I/O Ports
RapidConfigure Write Enable (WE) and Write Strobe (STROBE)
Hardware Reset
Device Reset
JTAG Pins
For downloading the serial configuration bitstream
TRST*
TRST*
TRST*
TRST*
I
TDI, TMS, TCK,
TDO
TDI, TMS,
TCK,
TDO
TDI, TMS,
TCK,
TDO
TDI, TMS,
TCK,
TDO
I
I
O
RCE
RCE
RCE
RCE
I
RapidConfigure Enable Pin
For Enabling RapidConfigure interface after reset
Power & Ground Pins
Power Pins for Group 1 I/O Buffer Drivers.
Power Pins for Group 2 I/O Buffer Drivers.
Power Pins for Group 3 I/O Buffer Drivers.
Power Pins for Group 4 I/O Buffer Drivers.
V
DD
.PAD1
V
DD
.PAD2
V
DD
.PAD3
V
DD
.PAD4
V
DD
.PAD1
V
DD
.PAD2
V
DD
.PAD3
V
DD
.PAD4
V
DD
.PAD1
V
DD
.PAD2
V
DD
.PAD1
V
DD
.PAD2
P
P
P
P
Table 12. IQX Pin Summary
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