參數(shù)資料
型號(hào)： IQX320-12PP391
英文描述： User Programmable Special Function ASIC
中文描述： 用戶可編程ASIC的特殊功能
文件頁(yè)數(shù)： 33/65頁(yè)
文件大?。?/td> 620K
代理商： IQX320-12PP391
IQX Family Data Sheet
June 2000
Revision 5.0
33
5.6 AC Electrical Specifications for IQX160 and IQX128B
(T
A
= 0°C to 70°C, V
DD
= 5V±5%; V
DD
.PAD = 5V±5%, or V
DD
.PAD = 3.3V±10%. Assume two I/O Ports connected through the
Switch Matrix with 35 pF external loading.)
Speed Grade
-7
-10
Units
MHz
ns
ns
ns
ns
MHz
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Mb/s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Ref.
Figure
Symbol
Parameter
Min
Max
133
Min
Max
100
f
RIO
t
W-RIO
t
S-RIO
t
H-RIO
t
CO-RIO
f
RI
t
W-RI
t
S-RI
t
H-RI
t
CO-RI
f
RO
t
W-RO
t
S-RO
t
H-RO
t
CO-RO
t
PHL
, t
PLH
t
BR
t
SK
t
W+
t
W-
R
DATA
t
PZH-IT
, t
PZL-IT
t
PZH-OT
, t
PZL-OT
t
PHZ-OT
, t
PLZ-OT
t
W-LI
t
S-LI
t
H-LI
t
CO-LI
t
P-LIT
t
W-LO
t
S-LO
t
H-LO
t
CO-LO
t
P-LOT
t
KW-RI
t
KS-RI
t
KH-RI
t
KCO-RI
Register Input/Output, Clock Frequency
(1, 2)
Register Input/Output, Clock Pulse Width, Low or High
(1, 2)
Register Input/Output, Data Setup Time to CLK
Register Input/Output, CLK to Data Hold Time
Register Input/Output, Clock to Output Data Valid
Register Input, Clock Frequency
(1)
Register Input, Clock Pulse Width, Low or High
Register Input, Data Setup Time to CLK
Register Input, CLK to Data Hold Time
Register Input, Clock to Output Data Valid
Register Output, Clock Pulse Frequency
(1)
Register Output, Clock Width, Low or High
Register Output, Data Setup Time to CLK
Register Output, CLK to Data Hold Time
Register Output, Clock to Output Data Valid
One Way Signal Propagation Delay
Additional Delay in Bus Repeater (BR) Mode
(1, 2)
Skew Between Output Ports
(1)
Input Flow Through Positive Pulse Width
(2)
Input Flow Through Negative Pulse Width
(2)
NRZ Data Rate
(1, 2)
Input Enable (GT) to Data Valid
Output Enable (GT) to Data Valid
Output Enable (GT) to Output at High Z
(1)
Latch Input, Latch Enable (GC) Pulse Width, Low or High
Latch Input, Data Setup Time to Latch Enable (GC) Trailing Edge
Latch Input, Data to Latch Enable (GC) Trailing Edge Hold Time
Latch Input, Latch Enable (GC) Leading Edge to Data Out Delay
Latch Input, Transparent Mode Propagation Delay
Latch Output, Latch Enable (GC) Pulse Width, Low or High
Latch Output, Data Setup Time to Latch Enable (GC) Trailing Edge
Latch Output, Data to Latch Enable (GC) Trailing Edge Hold Time
Latch Output, Latch Enable (GC) Leading Edge to Data Out Delay
Latch Output, Transparent Mode Propagation Delay
Register Input, MnimumPulse Width of KEY as Clock Enable, Low or High
Register Input, Clock Enable (Key) Setup Time to CLK (GC)
Register Input, CLK (GC) to Clock Enable (Key) Hold Time
Register Input, Key Clock to Output Data Valid
3.3
2.0
0.0
4.5
3.0
0.0
13
8.5
100
10.0
80
3.3
2.0
0.0
4.5
3.0
0.0
14
12.0
133
15.0
100
3.3
3.0
0.0
4.5
4.0
0.0
15
8.5
7.5
0.0
1.5
10.0
10.0
0.0
1.5
3.5
4.5
4.5
5.0
16
200
10.0
9.0
7.0
180
12.5
10.0
8.5
17
18
3.3
2.0
4.0
4.5
3.0
4.0
19
12.0
9.0
15.0
10.0
3.3
4.0
0.0
4.5
5.0
0.0
20
35.0
8.0
40.0
10.0
5.0
2.5
2.0
6.0
3.0
2.0
21
10.5
13.0
Table 19. AC Electrical Specifications for IQX160 and IQX128B
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