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| 型號： | IQX320-12PP391 |
| 英文描述： | User Programmable Special Function ASIC |
| 中文描述： | 用戶可編程ASIC的特殊功能 |
| 文件頁數(shù)： | 11/65頁 |
| 文件大?。?/td> | 620K |
| 代理商： | IQX320-12PP391 |
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IQX Family Data Sheet
June 2000
Revision 5.0
11
Symbol
I/O Port Function
Mnemonic
IN
Input
- The external signal is buffered fromthe I/O Port pin to the corresponding Switch Matrix
line. In this mode an optional input enable (IE) can be selected. Either polarity can be selected
for IE. The default level is a logic 1.
Registered Input (
with variable length shift register and inversion) - The external signal at the
I/O Port pin is registered into a 7-bit edge-triggered shift register within the I/O Port. An 8-to-1
mux selects either the input (bit 0) or one of the 7 output bits of the shift register and connects
it to the corresponding signal line in the Switch Matrix through a register. Any tap on the shift
register can be selected. The true or complement of the incomng signal can be selected. The
default is bit 0, true value. A clock source is required in this mode. Either edge of CLK can be
selected. The default for CLK is rising edge. A clock enable (CKE) and input enable (IE) are
also available but not required. Either polarity can be selected for IE and CKE. The default
level for IE and CKE is a logic 1. The outputs of the shift register are unknown after hardware
reset (TRST*= 0).
RI&
[bit = value]&
[INV = value]
Latched Input
- The external signal at the I/O Port pin is latched by a level-sensitive flip-flop
within the I/O Port. A latch enable source is required in this mode. The latch enable source is
composed of CLK and CKE, and at least one must be specified. An input enable (IE) is also
available but not required. Either polarity can be selected for CLK, CKE and IE. The default
level for all three is a logic 1. The output of the flip-flop is unknown after hardware reset
(TRST*= 0).
LI
Output
- The internal signal is buffered fromthe corresponding Switch Matrix line to the I/O
Port pin. In this mode an optional output enable (OE) can be selected. Either polarity can be
selected for OE. The default level is a logic 0.
OP
Latched Output
- The internal signal on the Switch Matrix line is latched by a level-sensitive
flip-flop within the I/O Port. A latch enable source is required in this mode. The latch enable
source is composed of CLK and CKE, and at least one must be specified. An output enable
(OE) is also available but not required. Either polarity can be selected for CLK and CKE. The
default level for both is a logic 1. Either polarity can be selected for OE. The default level is a
logic 0. The output of the flip-flop is unknown after hardware reset (TRST*= 0).
LO
Registered Output
- The internal signal on the Switch Matrix line is registered by an edge-
triggered flip-flop within the I/O Port. A clock source is required in this mode. Either edge of
CLK can be selected. The default for CLK is rising edge. A clock enable (CKE) and output
enable (OE) are also available but not required. Either polarity can be selected for CKE and
OE. The default level for CKE is a logic 1 and the default level for OE is a logic 0. The output
of the flip-flop is unknown after hardware reset (TRST*= 0).
RO
Bidirectional Transceiver
- In this mode, the I/O buffer acts as a bidirectional transceiver
between the I/O Port pin and the corresponding Switch Matrix line. This mode requires an
input enable (IE) and output enable (OE). Either polarity can be selected for each but the
default level for IE is a logic 1 and the default level for OE is a logic 0. When the same source
(with default polarities) is used for IE and OE, it effectively acts as direction control. When the
same control signal (with one polarity inverted) is used for IE and OE, it effectively acts as a
Bus Repeater (BR) (see below) when both are enabled, and as No Connect (NC) when neither
is enabled.
BT
Table 1. Summary of Programmable I/O Attributes for IQX Devices
Px
Ax
IE
CKE
Px
Ax
CLK
7
D Q
0
0
1
CE
0
7
IE
D
LE
Q
CKE
CLK
Px
Ax
IE
Px
Ax
OE
D
LE
Q
CKE
CLK
Px
Ax
OE
D
CE
Q
CKE
CLK
Px
Ax
OE
Px
Ax
IE
OE
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