參數(shù)資料
型號(hào)： IQX320-10PB416
英文描述： User Programmable Special Function ASIC
中文描述： 用戶(hù)可編程ASIC的特殊功能
文件頁(yè)數(shù)： 9/65頁(yè)
文件大?。?/td> 620K
代理商： IQX320-10PB416
IQX Family Data Sheet
June 2000
Revision 5.0
9
1.0 A
RCHITECTURE
IQX devices are SRAM-based bit-oriented switching matrices.
The devices can be configured and controlled in-systemby
storing appropriate data into the internal SRAM cells and
configuration registers. As shown in Figure 1, the main functional
blocks of the device are the non-blocking Switch Matrix,
Programmable
I/O
Ports,
RapidConfigure Configuration Interface and a JTAG-based
Configuration Controller.
I/O
Control
signal
block,
The full-featured programmable I/O Ports are connected to the
corresponding lines in the Switch Matrix. The I/O Port control
signals such as clock, clock enable, input enable, and output
enable are used to control the flow of data through the I/O Ports.
The JTAG-based configuration controller is used to download the
configuration bit streamserially into the I/O Port configuration
registers and Switch Matrix SRAM cells, thereby establishing the
desired functional attributes for the I/O Ports and connections
among themthrough the Switch Matrix. Alternatively, the
RapidConfigure parallel interface may be used to load the
configuration data in the I/O Port Configuration Registers and
Switch Matrix SRAMcells. The use of RapidConfigure interface
enables quick configuration changes.
1.1 Non-blocking Switch Matrix
The Switch Matrix is an x-y routing structure (or grid). Each
horizontal signal trace is
hardwired
to a corresponding vertical
signal trace as shown by the junction dots in Figure 2. An I/O
Port pin connects to this horizontal-vertical trace pair through a
programmable buffer. Signal paths through the Switch Matrix are
very well balanced, resulting in predictable and uniformpin-to-
pin delays.
A pass transistor whose ON/OFF state is controlled by a
dedicated SRAMcell is placed at the intersection of two different
signal lines. Signal multicasting/broadcasting operation is
supported by allowing a Switch Matrix line carrying an incomng
signal to be connected to multiple Switch Matrix lines carrying
outgoing signals. Signal multiplexing is supported by allowing
multiple Switch Matrix lines carrying incomng signals (controlled
using input enable signals) to be connected to the same Switch
Matrix line carrying an outgoing signal. It is also possible to
create a common internal node among multiple Switch Matrix
lines by making all pair-wise connections among these signal
lines, and driving such a node by configuring the corresponding
I/O Ports in the Bus Repeater mode. Refer to the section on “I/O
Port Functional Mode” for more details.
Figure 2. Switch Matrix Structure
1.1.1 Switch Control
As shown in Figure 3, there are two possible switch and SRAM
cell locations for a connection between any two Switch Matrix
lines. For example, the two possible switch (and SRAMcell)
locations controlling a connection between signal lines i and j are
row i (word i) and column j (bit j), or row j and column i. Only one
location is populated with a switch and the controlling SRAM
cell. This location is called the
real
location while the other one
is referred to as the
ghost
location. The real cell locations forma
unique pattern on the device die as described in Appendix A.
The section on “RapidConfigure Interface” explains how this
knowledge can be used to reduce the time it takes to change
Switch Matrix connections.
1
0
2
3
4
5
6
7
I/O Port Pins
SRAM
Cells
Pass
Transistors
Signal
Lines
Permanent
Connections
Programmable I/O Buffers
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