- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360914 > IQX320-10PB416 User Programmable Special Function ASIC PDF資料下載
參數(shù)資料
| 型號： | IQX320-10PB416 |
| 英文描述： | User Programmable Special Function ASIC |
| 中文描述： | 用戶可編程ASIC的特殊功能 |
| 文件頁數(shù)： | 12/65頁 |
| 文件大小： | 620K |
| 代理商： | IQX320-10PB416 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁
IQX Family Data Sheet
12
Revision 5.0
June 2000
Bidirectional Transceiver with Latched Input
- This mode combines Latched Input (LI) and
output buffer (OP). A latch enable source is required in this mode. The latch enable source is
composed of CLK and CKE, and at least one must be specified. Either polarity can be selected
for CLK and CKE. The default level for both is a logic 1. This mode also requires an input
enable (IE) and output enable (OE). Either polarity can be selected for IE and OE. The default
level for IE is a logic 1 and the default level for OE is a logic 0. The output of the flip-flop is
unknown after hardware reset (TRST*= 0).
BT&LI
Bidirectional Transceiver with Registered Input
- This mode combines Registered Input
with programmable tap and inversion (RI) and buffered Output (OP). A clock source is required
in this mode. Either edge of CLK can be selected. The default for CLK is rising edge. A clock
enable (CKE) is available but not required. Either polarity can be selected. The default level for
CKE is a logic 1. This mode also requires an input enable (IE) and output enable (OE). Either
polarity can be selected for each. The default level for IE is a logic 1 and the default level for
OE is a logic 0. The output of the flip-flop is unknown after hardware reset (TRST*= 0).
BT&RI&
[bit = value]&
[INV = value]
Bidirectional Transceiver with Latched Output
- This mode combines Latched Output (LO)
and input buffer (IN). A latch enable source is required in this mode. The latch enable source
is composed of CLK and CKE. At least one must be specified. Either polarity can be selected
for CLK and CKE. The default level for both is a logic 1. This mode also requires an input
enable (IE) and output enable (OE). Either polarity can be selected for IE and OE. The default
level for IE is a logic 1 and the default level for OE is a logic 0. The output of the flip-flop is
unknown after hardware reset (TRST*= 0).
BT&LO
Bidirectional Transceiver with Registered Output
- This mode combines Registered Output
(RO) and buffered Input (IN). A clock source is required in this mode. Either edge of CLK can
be selected although the default is rising edge. A clock enable (CKE) is available but not
required. Either polarity can be selected but the default level is a logic 1. This mode also
requires an input enable (IE) and output enable (OE). Either polarity can be selected for IE and
OE. The default level for IE is a logic 1 and the default level for OE is a logic 0. The output of
the flip-flop is unknown after hardware reset (TRST*= 0).
BT&RO
Bidirectional Transceiver with Registered I/O
- This mode is a combination of Registered
Input (RI) with programmable tap and inversion, and Registered Output (RO). A clock source
is required in this mode. Either edge of CLK can be selected. The default is rising edge. A
clock enable (CKE) is available but not required. Either polarity can be selected for CKE. The
default level is a logic 1. This mode also requires an input enable (IE) and output enable (OE).
Either polarity can be selected for IE and OE. The default level for IE is a logic 1 and the
default level for OE is a logic 0. The output of the flip-flops is unknown after hardware reset
(TRST*= 0).
BT&RI&
[bit = value]&
[INV = value]
&RO
Other BT Modes
- Other combinations of I/O Port modes (not covered in this table) are less
likely but can be used. The mnemonic is BT [&RI |&LI] [&RO |&LO], where the specification
inside the brackets “[ ]” is optional and “| stands for either or. Insure that control signal
requirements are met. In these modes, the output of the flip-flops is unknown after hardware
reset (TRST*= 0).
Symbol
I/O Port Function
Mnemonic
Table 1. Summary of Programmable I/O Attributes for IQX Devices (Continued)
D
LE
Q
CKE
CLK
IE
Px
Ax
OE
Px
Ax
OE
CKE
CLK
7
D Q
0
0
1
CE
0
7
IE
D
LE
Q
CKE
CLK
Px
Ax
IE
OE
Px
Ax
IE
OE
CE
CKE
CLK
D
Q
D
I
CE
Q
O
Q
I
D
O
Px
Ax
IE
OE
CKE
CLK
7
0
0
1
0
7
Powered by ICminer.com Electronic-Library Service CopyRight 2003
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IQX320-10PP391 | User Programmable Special Function ASIC |
| IQX320-10PP391I | User Programmable Special Function ASIC |
| IQX320-12PP391 | User Programmable Special Function ASIC |
| IQX320-12PP391I | User Programmable Special Function ASIC |
| IQX320-15PP391 | User Programmable Special Function ASIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IQXO-22C-24.0 | 制造商:IQD Frequency Products 功能描述:OSCILLATOR CRYSTAL |
| IQXO-22C-32MHZ | 制造商:IQD Frequency Products 功能描述:OSCILLATOR CRYSTAL |
| IQXO-22C-4.0 | 制造商:IQD Frequency Products 功能描述:OSCILLATOR CRYSTAL |
| IQXO-22C-50.0 | 制造商:IQD Frequency Products 功能描述:OSCILLATOR CRYSTAL |
| IQXO-331-100.0MHz | 制造商:IQD Frequency Products 功能描述:CRYSTAL OSCILLATOR 100.000000MHZ |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。