參數(shù)資料
型號(hào)： IQX160-7PQ208
英文描述： User Programmable Special Function ASIC
中文描述： 用戶(hù)可編程ASIC的特殊功能
文件頁(yè)數(shù)： 23/65頁(yè)
文件大?。?/td> 620K
代理商： IQX160-7PQ208
IQX Family Data Sheet
June 2000
Revision 5.0
23
2.0 M
ISCELLANEOUS
D
ETAILS
2.1 Device Reset
To ensure proper operation, the device reset pin, TRST*must be
held low during power up. The reset pulse must be at least
200ns long. The IQX device is ready for configuration as soon
as it comes out of reset. The recommended reset circuitry is
shown in Figure 8, using an external supervisor device.
.
Figure 8. Reset Circuit
It should be noted that the TRST*pin must not be driven by any
devices which cannot guarantee a low signal during power-up.
Improper devices are those whose pins are either high or tri-
stated during power-up. Examples of such devices are SRAM-
based FPGAs.
When the device is in operation, different functional blocks can
be reset using one of following methods. Each method performs
a slightly different action as shown in Table 9.
In any of the reset methods the edge and level-sensitive flip-
flops in the I/O Port buffers are not cleared and will have
unknown output values.
2.2 Mixed Voltage Operation
There are multiple sources for power on the IQX device. The first
one called V
DD
is a 5V source and is used to power the device
core, including the Switch Matrix SRAMcells, I/O Port logic
(excluding the I/O buffer driver), I/O control logic, JTAG logic and
other circuitry. The I/O buffer drivers are powered by a different
source called V
DD
.PAD. The number of V
DD
.PAD sources
depends on the device. Table 13 shows the number of V
DD
.PAD
sources and the I/O Ports controlled by them The V
DD
.PAD pins
can be connected to either a 5V or 3V supply. This makes it
easy to interface IQX device to 5V and/or 3V logic levels.
2.3 Power Pin V
DD
.X
The IQX devices contain a pin marked V
DD
.X. The devices
contain an on-chip charge pump. In order for the charge pump to
operate correctly, it is required that the V
DD.x
pin be left floating
and completely unconnected. The charge pump should also be
left in its default “on’ setting. This is controlled by bit #6
(C_PUMP) of the mode control register.
Vdd
Ref
GND
RST
RST
PBRST
IQX
Supervisor
+5
Vmon
TRST*
Reset Method
Switch
Matrix
Cleared
Cleared
Cleared
I/O Ports
Set to Input (IN) Set to Input (IN)
Set to Input (IN) Set to Input (IN)
Set to Input (IN) Set to Input (IN)
I/O Config.
Holding
Register
JTAG
State
Machine
Reset
Unchanged Enabled if RCE pin = 1
Unchanged Stays Enabled
RapidConfigure
Interface
Enabled if RCE pin = 1
Pulsing TRST*low
Shifting in the “Device Reset” instruction using JTAG
Applying “I/O Port and Switch Matrix Reset” instruction using RapidConfigure
interface
Applying “Switch Matrix Reset” instruction using RapidConfigure interface
Cleared
Unchanged
Unchanged
Unchanged Stays Enabled
Table 9. Device Reset
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