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| 型號： | IQX160-7PQ208 |
| 英文描述： | User Programmable Special Function ASIC |
| 中文描述： | 用戶可編程ASIC的特殊功能 |
| 文件頁數(shù)： | 21/65頁 |
| 文件大?。?/td> | 620K |
| 代理商： | IQX160-7PQ208 |
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IQX Family Data Sheet
June 2000
Revision 5.0
21
1.4.4 I/O Port Configuration Register Contents
Note:
*User defined value
Each programmable I/O Port on the IQX device contains a 50-bit
Configuration Register. The function of an I/O Port is determned
by the contents of its configuration register. Table 7 shows the
contents for the different I/O functions. Combinations that are not
listed are illegal and may result in improper operation or damage
to the device.
The bits in Table 7 indicated by a “*” refer to the values and
polarity of the various control sources and must be filled in
correctly based on the user selection of the control sources.
1.4.5 Reset Commands
The RapidConfigure interface can also be used to quickly clear
the Switch Matrix and reset the I/O Ports to their default state.
Refer to the table below for details. When RapidConfigure is
used for resetting the I/O Ports the contents of the configuration
holding register are set to the default state shown in Table 8,
however the contents of the Mode Control Register and the state
of the JTAG controller are not affected.
I/O Mode
Mnemon
ic
Seg 6
Bit
76543210
Seg 5
Bit
76543210
Seg 4
Bit
76543210
Seg 3
Bit
76543210
Seg 2
Bit
76543210
Seg 1
Bit
76543210
Seg 0
Bit
76543210
.
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
.
.
.
.
.
.
.
.
11000110
11000110
11000110
11000110
11000110
11000110
11000110
11000110
11000110
11000110
11000110
11000110
11000110
11000110
11000110
11000110
11000110
11000110
11000110
11000110
11000110
11000110
110**111
11000110
.
N
P
P
I
I
B
D
00000000
00000000
000*****
000*****
000*****
********
********
00000000
000*****
000*****
000*****
00000000
000*****
00000000
000*****
000*****
000*****
000*****
00000000
00000000
00000000
00000000
00000000
00000000
D
D
K
K
K
K
K
.
00011111
00011111
00011111
00******
00******
0*******
0*******
00011111
00011111
00******
00******
00******
00******
00111111
00******
00******
00******
00******
00011111
00011111
00011111
00011111
00011111
00011111
I
I
I
C
C
C
C
R
00001111
00001111
00001111
0010****
0010****
1000****
1000****
00001111
00001111
0001****
0001****
0100****
0100****
00001111
0010****
1000****
0001****
0100****
00001111
00001111
00001111
00001111
00001111
00001111
R
L
L
C
C
C
C
F
00011111
00011111
00011111
00011111
00011111
00011111
00011111
00101111
001*****
00101111
001*****
00001111
000*****
001*****
001*****
001*****
001*****
000*****
01001111
10001111
00011111
00011111
00101111
00011111
F
O
I
O
O
O
O
A
00111111
00111111
001*****
00111111
001*****
00011111
00001111
000*****
00001111
00001111
00001111
00001111
00001111
001*****
001*****
000*****
001*****
001*****
00001111
00001111
01011111
10011111
00111111
00001111
A
I
I
I
I
I
I
Value After Reset
Input
Input w/ Tristate
Latched Input
Latched Input w/ Tristate
Registered Input
Registered Input w/ Tristate
Output
Output w/ Tristate
Latched Output
Latched Output w/ Tristate
Registered Output
Registered Output w/ Tristate
Bidirectional Transceiver
Bidirectional Transceiver w/ Latched Input
Bidirectional Transceiver w/ Registered Input
Bidirectional Transceiver w/ Latched Output
Bidirectional Transceiver w/ Registered Output
Pin Force 0
Pin Force 1
Array Force 0
Array Force 1
Bus Repeater
No Connect
IN
LI
RI
OP
LO
RO
BT
BT&LI
BT&RI
BT&LO
BT&RO
F0
F1
A0
A1
BR
NC
Table 7. I/O Configuration Register Contents
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