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參數(shù)資料
| 型號： | IPD2545A |
| 元件分類： | 顯示用LED |
| 英文描述： | 5X7 DOT MATRIX DISPLAY, HIGH EFFICIENCY RED, 6.4 mm |
| 封裝： | ROHS COMPLIANT, HERMETIC SEALED, CERAMIC PACKAGE-20 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 869K |
| 代理商： | IPD2545A |
IPD2545A, IPD2547A, IPD2548A
2006-03-03
9
Attributes are non-destructive. If a character with bit D7 set is
replaced by a cursor (Control Word bit D4 is set, and D3=D2=0)
the character will remain in memory and can be revealed again by
clearing D4 in the Control Word.
Blink (D5): The entire display can be caused to blink at a rate of
approximately 2.0 Hz by setting bit D5 in the Control Word. This blink-
ing is independent of the state of D7 in all character locations.
To synchronize the blink rate in a bank of these devices, it is nec-
essary to tie all devices' clocks and resets together as described in
a later section of this data sheet.
Lamp Test (D6): When the Lamp Test bit is set, all dots in the
entire display are lit at half brightness. When this bit is cleared, the
display returns to the characters that were showing before the
lamp test.
Cascading the Display
Clear Data (D7): When D7 (D7=1) is set in the Control Word, all
display memory bits are reset to zero. A second Control Word must
be written into the chip with D7 (D7=0) reset to set up attributes and
brightness levels.
Cascading
Cascading the display (Figure below) is a simple operation. The
requirements for cascading are:
1) decoding the correct address to determine the chip select for
each additional device,
2) assuring that all devices are reset simultaneously, and
3) selecting one display as the clock source and setting all others
to accept clock input (the reason for cascading the clock is to syn-
chronize the flashing of multiple displays). One display as a source
is capable of driving six other displays. If more displays are
required, a buffer will be necessary. The source display must have
pin 3 tied high to output clock signals. All other displays must have
pin 3 tied low.
Voltage Transients
It has become common practice to provide 0.01 F bypass capaci-
tors liberally in digital systems. Like other CMOS circuitry, the Intel-
ligent Display controller chip has very low power consumption and
the usual 0.01 F would be adequate were it not for the LEDs. To
prevent power supply transients, capacitors with low inductance
and high capacitance at high frequencies are required. This sug-
gests a solid tantalum or ceramic disc for high frequency bypass.
For larger displays, distribute the bypass capacitors evenly, keep-
ing capacitors as close to the power pins as possible. We recom-
mend a 10 F and 0.01 F for every Intelligent Display to decouple
the displays themselves, at the display.
D7
D6
D5
D4
D3
D2
D1
D0
Operation
0
X
B
Disable highlight
attribute
0
1
0
B
Display cursor*
instead of character
0
1
0
1
B
Blink single character
0
1
0
B
Display blinking cur-
sor* instead of char-
acter
0
1
B
Alternate character
with cursor*
*“Cursor”= all dots in a single character space lit to half brightness
X=don't care
B=depends on the selected brightness
D7
D6
D5
D4
D3
D2
D1
D0
Operation
0
1
X
B
Blinking display
D7
D6
D5
D4
D3
D2
D1
D0
Operation
0
1
0
X
Lamp test
D7
D6
D5
D4
D3
D2
D1
D0
Operation
1
0
X
Clear
CLK
SEL
V
WR
RD
CE0
CLK
I/O
RESET
D0-D7
A0-A2
CE1
CC
H
0.01 F
10 F
CLK
SEL
CE0
RD
WR
CE1
A0-A2
D0-D7
RESET
CLK
I/O
10
RD
CE1
CE0
A0-A2
WR
RESET
D0-D7
10
CLK
SEL
CLK
I/O
WR
CE1
CE0
RD
D0-D7
A0-A2
RESET
CLK
I/O
10
CLK
SEL
RESET
D0-D7
A0-A2
WR
RD
CC
V
VCC
616
5
48
3
2
1
74LS138
14
13
12
15
A3
A4
A5
20
CC
V
20
CC
V
20
CC
V
10
L
0.01 F
10 F
0.01 F
IDCD5039
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