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參數(shù)資料
| 型號(hào)： | IP82C89 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | CMOS Bus Arbiter |
| 中文描述： | 8 MHz, BUS ARBITER AND CONT SIG GEN, PDIP20 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大小： | 123K |
| 代理商： | IP82C89 |
4-351
TABLE 1. SUMMARY OF 82C89 MODES, REQUESTING AND RELINQUISHING THE MULTI-MASTER SYSTEM BUS
SINGLE LINES FROM
80C86 OR 80C88 OR 8088
IOB MODE
ONLY
IOB = LOW
RESB = LOW
RESB MODE ONLY
IOB = HIGH, RESB = HIGH
IOB MODE RESB MODE
IOB = LOW, RESB = HIGH
SINGLE BUS
MODE
IOB = HIGH
RESB = LOW
S2
S1
S0
SYSB/RESB =
HIGH
SYSB/RESB =
LOW
SYSB/RESB =
HIGH
SYSB/RESB =
LOW
I/O
Commands
0
0
0
0
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
Halt
0
1
1
X
X
X
X
X
X
Memory
Commands
1
1
1
0
0
1
0
1
0
X
X
X
X
X
X
Idle
1
1
1
X
X
X
X
X
X
NOTES:
1. X = Multi-Master System Bus is allowed to be Surrendered.
2. = Multi-Master System Bus is Requested.
MODE
PIN
STRAPPING
MULTI-MASTER SYSTEM BUS
REQUESTED**
SURRENDERED*
Single Bus Multi-Master Mode
IOB = High
RESB = Low
Whenever the processor’s status lines
go active
HLT + TI CBRQ + HPBRQ
RESB Mode Only
IOB = High
RESB = High
SYSB/RESB + High
ACTIVE STATUS
(SYSB/RESB = Low + TI)
CBRQ + HLT + HPBRQ
IOB Mode Only
IOB = Low
RESB = Low
Memory Commands
(I/O Status + TI) CBRQ + HLT +
HPBRQ
IOB Mode RESB Mode
IOB = Low
RESB = High
(Memory Command)
(SYSB/RESB = High)
(I/O Status Commands) +
SYSB/RESB = Low) CBRQ +
HPBRQ + HLT
NOTES:
* LOCK prevents surrender of Bus to any other arbiter, CRQLCK prevents surrender of Bus to any lower priority arbiter.
** Except for HALT and Passive or IDLE Status.
HPBRQ, Higher priority Bus request or BPRN = 1.
1. IOB Active Low.
2. RESB Active High.
3. + is read as “OR” and as “AND”
4. TI = Processor Idle Status S2, S1, S0 = 111
5. HLT = Processor Halt Status S2, S1, S0 = 011
82C89
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