VCC = 5.0V ±10%; T
參數(shù)資料
型號(hào)： IP80C88
廠商： Intersil
文件頁(yè)數(shù)： 9/38頁(yè)
文件大小： 0K
描述： IC CPU 8/16BIT 5V 5MHZ 40-DIP
標(biāo)準(zhǔn)包裝： 99
處理器類(lèi)型： 80C88 8/16-位
速度： 5MHz
電壓： 4.5 ~ 5.5V
安裝類(lèi)型： 通孔
封裝/外殼： 40-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 40-DIP
包裝： 管件
17
FN2949.4
February 22, 2008
AC Electrical Specifications
VCC = 5.0V ±10%; TA = 0°C to +70°C (C80C88, C80C88-2)
VCC = 5.0V ±10%; TA = -40°C to +85°C (I80C88, I80C88-2)
VCC = 5.0V ±10%; TA = -55° to +125°C (M80C88)
SYMBOL
PARAMETER
TEST
CONDITIONS
80C88
80C88-2
UNITS
MIN
MAX
MIN
MAX
MINIMUM COMPLEXITY SYSTEM
Timing Requirements
(1)
TCLCL
CLK Cycle Period
200
-
125
-
ns
(2)
TCLCH
CLK Low Time
118
-
68
-
ns
(3)
TCHCL
CLK High Time
69
-
44
-
ns
(4)
TCH1CH2
CLK Rise Time
From 1.0V to 3.5V
-
10
-
10
ns
(5)
TCL2CL1
CLK FaIl Time
From 3.5V to 1.0V
-
10
-
10
ns
(6)
TDVCL
Data In Setup Time
30
-
20
-
ns
(7)
TCLDX1
Data In Hold Time
10
-
10
-
ns
(8)
TR1VCL
RDY Setup Time into 82C84A
(Notes 6,7)
35
-
35
-
ns
(9)
TCLR1X
RDY Hold Time into 82C84A
(Notes 6,7)
0-
0
-
ns
(10)
TRYHCH
READY Setup Time into 80C88
118
-
68
-
ns
(11)
TCHRYX
READY Hold Time into 80C88
30
-
20
-
ns
(12)
TRYLCL
READY Inactive to CLK (Note 8)
-8
-
-8
-
ns
(13)
THVCH
HOLD Setup Time
35
-
20
-
n
s
(14)
TINVCH
lNTR, NMI, TEST Setup Time
(Note 7)
30
-
15
-
ns
(15)
TILIH
Input Rise Time (Except CLK)
From 0.8V to 2.0V
-
15
-
15
ns
(16)
TIHIL
Input FaIl Time (Except CLK)
From 2.0V to 0.8V
-
15
-
15
ns
Timing Responses
(17)
TCLAV
Address Valid Delay
CL = 100pF
10
110
10
60
ns
(18)
TCLAX
Address Hold Time
CL = 100pF
10
-
10
-
ns
(19)
TCLAZ
Address Float Delay
CL = 100pF
TCLAX
80
TCLAX
50
ns
(20)
TCHSZ
Status Float Delay
CL = 100pF
-
80
-
50
ns
(21)
TCHSV
Status Active Delay
CL = 100pF
10
110
10
60
ns
(22)
TLHLL
ALE Width
CL = 100pF
TCLCH-20
-
TCLCH-10
-
ns
(23)
TCLLH
ALE Active Delay
CL = 100pF
-
80
-
50
ns
(24)
TCHLL
ALE Inactive Delay
CL = 100pF
-
85
-
55
ns
(25)
TLLAX
Address Hold Time to ALE
Inactive
CL = 100pF
TCHCL-10
-
TCHCL-10
-
ns
(26)
TCLDV
Data Valid Delay
CL = 100pF
10
110
10
60
ns
(27)
TCLDX2
Data Hold Time
CL = 100pF
10
-
10
-
ns
(28)
TWHDX
Data Hold Time After WR
CL = 100pF
TCLCL-30
-
TCLCL-30
-
ns
(29)
TCVCTV
Control Active Delay 1
CL = 100pF
10
110
10
70
ns
(30)
TCHCTV
Control Active Delay 2
CL = 100pF
10
110
10
60
ns
(31)
TCVCTX
Control Inactive Delay
CL = 100pF
10
110
10
70
ns
(32)
TAZRL
Address Float to READ Active
CL = 100pF
0
-
0
-
ns
80C88
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IP80C88/+ 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:16-Bit Microprocessor
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