21
FN2949.4
February 22, 2008
AC Electrical Specifications
VCC = 5.0V±10%; TA = 0°C to +70°C (C80C88, C80C88-2)
VCC = 5.0V±10%; TA = -40°C to +85°C (I80C88, I80C88-2)
VCC = 5.0V±10%; TA = -55°C to +125°C (M80C88)
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)
SYMBOL
PARAMETER
TEST CONDITIONS
80C88
80C88-2
UNITS
MIN
MAX
MIN
MAX
TIMING REQUIREMENTS
(1)
TCLCL
CLK Cycle Period
200
-
125
-
ns
(2)
TCLCH
CLK Low Time
118
-
68
-
ns
(3)
TCHCL
CLK High Time
69
-
44
-
ns
(4)
TCH1CH2
CLK Rise Time
From 1.0V to 3.5V
-
10
-
10
ns
(5)
TCL2CL1
CLK Fall Time
From 3.5V to 1.0V
-
10
-
10
ns
(6)
TDVCL
Data in Setup Time
30
-
20
-
ns
(7)
TCLDX1
Data In Hold Time
10
-
10
-
ns
(8)
TR1VCL
RDY Setup Time into 82C84
35
-
35
-
ns
(9)
TCLR1X
RDY Hold Time into 82C84
0-
0
-
ns
(10)
TRYHCH
READY Setup Time into 80C88
118
-
68
-
ns
(11)
TCHRYX
READY Hold Time into 80C88
30
-
20
-
ns
(12)
TRYLCL
READY Inactive to CLK (N
ote15)-8
-
-8
-
ns
(13)
TlNVCH
Setup Time for Recognition
(lNTR, NMl, TEST) (Note
14)30
-
15
-
ns
(14)
TGVCH
RQ/GT Setup Time
30
-
15
-
ns
(15)
TCHGX
RQ Hold Time into 80C88 (Note
16)40
TCHCL +
10
30
TCHCL +
10
ns
(16)
TILlH
Input Rise Time (Except CLK)
From 0.8V to 2.0V
-15
ns
(17)
TIHIL
Input Fall Time (Except CLK)
From 2.0V to 0.8V
-15
ns
TIMING RESPONSES
(18)
TCLML
Command Active Delay (Note
CL = 100pF
for all 80C88 outputs in
addition
to
internal
loads.
5
35535
ns
(19)
TCLMH
Command Inactive (Note
5
35535
ns
(20)
TRYHSH
READY Active to Status Passive
(Notes
-110
-
65
ns
(21)
TCHSV
Status Active Delay
10
110
10
60
ns
(22)
TCLSH
Status Inactive Delay (Note
17)10
130
10
70
ns
(23)
TCLAV
Address Valid Delay
10
110
10
60
ns
(24)
TCLAX
Address Hold Time
10
-
10
-
ns
(25)
TCLAZ
Address Float Delay
TCLAX
80
TCLAX
50
ns
(26)
TCHSZ
Status Float Delay
-
80
-
50
ns
(27)
TSVLH
Status Valid to ALE High (Note
20
-
20
ns
(28)
TSVMCH
Status Valid to MCE High (Note
30
-
30
ns
(29)
TCLLH
CLK Low to ALE Valid (Note
20
-
20
ns
(30)
TCLMCH
CLK Low to MCE High (Note
25
-
25
ns
(31)
TCHLL
ALE Inactive Delay (Note
4
18418
ns
80C88