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參數(shù)資料
| 型號(hào)： | IMICB660EYB |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 117K |
| 代理商： | IMICB660EYB |
CB660
I
2
C System Clock Buffer for Mobile Applications
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
2/2/98
Page 2 of 8
PIN DESCRIPTION
TYPE
PIN
No.
9
Pin
Name
FIN
PWR
I/O
Description
-
I
PAD
This pin is connected to the input reference clock. This
clock must be in the range of 10.0 to 100.0 Mhz.
Low skew output clock .
Low skew output clock .
Low skew output clock .
Low skew output clock .
Low skew output clock .
Low skew output clock .
Buffer Output Enable pin. This pin is low it is used to place
all output clocks (CLK1:10) in a tri state condition. This
feature facilitates in production board level testing to be
easily implemented for the clocks that this device produces.
Has internal pull-up resistor.
Serial data of I
2
C 2-wire control interface. Has internal pull-
up resistor.
Serial clock of I
2
C 2-wire control interface. Has internal
pull-up resistor.
Ground pins for clock output buffers. These pins must be
returned to the same potential to reduce output clock skew.
2,3
6, 7
11
18
22, 23
26,27
20
SDRAM(0:1)
SDRAM(2:3)
SDRAM4
SDRAM5
SDRAM(6:7)
SDRAM(8:9)
OE
VDDB
VDDB
VDDB
VDDB
VDDB
VDDB
-
O
O
O
O
O
O
I
BUF1
BUF1
BUF1
BUF1
BUF1
BUF1
PAD
14
SDATA
VDD
I/O
PAD
15
SCLOCK
VDD
I
PAD
4, 8, 12,
16, 17,
21, 25
1, 5, 10,
19, 24,
28
13
VSS
PWR
-
VDDB
-
PWR
-
Power for output clock buffers.
VDD
-
PWR
-
Pin for device core logic.
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