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參數(shù)資料
| 型號： | IMICB660EYB |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 117K |
| 代理商： | IMICB660EYB |
CB660
I
2
C System Clock Buffer for Mobile Applications
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
2/2/98
Page 1 of 8
PRODUCT FEATURES
10 output buffer for high clock fanout applications
Each output can be internally disabled for EMI and
power consumption reduction.
Separate power supply for each group of 2 clock
outputs for mixed voltage application.
< 250ps skew between output clocks.
28-pin SSOP & TSSOP packages for minimum
boad space
Single Clock Enable pin for testability
BLOCK DIAGRAM
VDDB
OE
SDATA
SCLOCK
SDRAM(2:3)
VDD
FIN
I2C
SDRAM(0:1)
SDRAM4
SDRAM5
SDRAM(8:9)
SDRAM(6:7)
PRODUCT DESCRIPTION
The device is a high fanout system clock regenerator.
Its primary application is to create the large quantity of
clocks needed to support a wide range of applications
that require a large number of clock loads that are
referenced to a single existing clock. Loads of up to 30
pF are supported. One of the chief applications of this
component is where long traces are used to transport
clocks from their generating devices to their loads.
The creation of EMI and the degradation of waveform
rise and fall times is greatly reduced by running a
single reference clock trace to this device and then
using it to regenerate the clock that drives shorter
traces by using the IMICB660 to generate the clocks at
the target devices EMI is therefore minimized and
board real estate is saved.
CONNECTION DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VDDB
SDRAM9
SDRAM8
VSS
VDDB
SDRAM7
SDRAM6
VSS
OE
VDDB
SDRAM5
VSS
VSS
SCLOCK
VDDB
SDRAM0
SDRAM1
VSS
VDDB
SDRAM2
SDRAM3
VSS
FIN
VDDB
SDRAM4
VSS
VDD
SDATA
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