參數(shù)資料
型號(hào): IMIB9680AYB
元件分類: 時(shí)鐘及定時(shí)
英文描述: LOW SKEW CLOCK DRIVER, PDSO48
文件頁(yè)數(shù): 1/8頁(yè)
文件大?。?/td> 103K
代理商: IMIB9680AYB
B9680
I
2C System Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC.
Rev 1.0
6/10/1999
525 LOS COCHES ST., MILPITAS, CA 95035, USA
Page 1 of 8
TEL: 408-263-6300. FAX 408-263-6571
WWW.IMICORP.COM
Product Features
S
18 output buffer for high clock fanout applications
S
Each output can be disabled Through I
2C
S
3.3Volts typical operation supply
S
Frequency range 10 Mhz to 166.6 Mhz
S
< 250ps skew between output clocks
S
48-pin SSOP package
S
Tri-state enable for system testing.
Block Diagram
CLK[1:2]
CLK[3:4]
VDD
CLK[5:6]
CLK[7:8]
CLK[9:10]
CLK[17,18]
SDATA
SCLK
CLK[11:12]
CLK[13:14]
CLK[15:16]
VDD
Control
Logic
OE
VDD
REFIN
VDDC
Product Description
The IMI B9680 is a high fanout system clock buffer. Its
primary application is to create the large quantity of
clocks needed to support a wide range of applications
that
requires
those
clock
loads
signal
that
are
referenced to a single existing clock. Loads of up to 30
pF are supported. The main application of
this
component is to redistribute SDRAM clocks from their
generating devices typically the 440BX chipset to their
loads, the SDRAM modules. The creation of EMI and
the degradation of waveform rise and fall times is
greatly reduced by running a single reference clock
trace to this device and then using it to regenerate the
clock that drives shorter traces. Using these devices
EMI is therefore minimized and board layout is
simplified.
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
NC
VDD
CLK1
CLK2
VSS
VDD
CLK3
CLK4
VDD
CLK5
CLK6
VDD
CLK7
VSS
CLK8
VSS
CLK9
VSS
VDDC
SDATA
SCLOCK
VSSC
VSS
CLK10
VDD
VSS
VDD
CLK13
CLK14
OE
VSS
CLK16
VDD
CLK12
VSS
VDD
CLK15
VSS
CLK17
CLK18
VDD
NC
VDD
REFIN
CLK11
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