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參數(shù)資料
| 型號(hào)： | IMISC611XYB |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 75 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO34 |
| 封裝： | SSOP-34 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 249K |
| 代理商： | IMISC611XYB |
IMISC611
SYSTEM CLOCK CHIP
Preliminary, May, 1996
CMOS PLL
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Page 1 of 7
PRODUCT FEATURES
T Supports Pentium and Cyrix CPU’s.
T 8 host (CPU) clocks for additional SDRAM support.
T Optional common or mixed supply mode :
(VDD = B1VDD = B2VDD = 2.5V)
(VDD = B1VDD = B2VDD = 3.3V)
(VDD = 3.3V, B1VDD = B2VDD = 2.5V)
(VDD = 3.3V, B1VDD = 3.3V, B2VDD = 2.5V)
(VDD = 3.3V, B1VDD = 2.5V, B2VDD = 3.3V)
T < 250 pS skew on CPU buffers
T < 250 pS skew on PCI buffers
T 60 mA buffer switching current
T 34 Pin SSOP package for minimum board space
BLOCK DIAGRAM
FREQUENCY TABLE
S2
S1
S0
CPU
PCI
0
50
33.3
0
1
55
36.67
0
1
0
TEST
0
1
75
37.5
10
0
50
25
1
0
1
55
27.6
11
0
60
30
1
66.6
33.3
CONNECTION DIAGRAM
APPLICATIONS
Pentium
or Cyrix CPU’s with any available chipset
support for PCI systems.
VDD
REF
VSS
n/c
VSS
PCI1
PCI2
PCI3
VDD
PCI4
PCI5
PCI6
S2
TS#
AVSS
LF1
AVDD
XIN
XOUT
VSS
B2VDD
CPU8
CPU7
CPU6
CPU5
VSS
CPU4
CPU3
CPU2
CPU1
B1VDD
S0
S1
VSS
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
REF
PLL
S2
S1
S0
REF
XIN
XOUT
B
PCI(1:6)
6
B
CPU(1:4)
B1VDD
4
LF1
B
CPU(5:8)
4
B2VDD
dly
TS#
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