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參數(shù)資料
| 型號： | IMC064FLSG |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5 V Series 200 Flash Memory Card(5V系列200閃速存儲器插卡) |
| 中文描述： | 64M X 8 FLASH 5V PROM CARD, 200 ns, XMA68 |
| 封裝： | PC CARD |
| 文件頁數(shù)： | 9/35頁 |
| 文件大?。?/td> | 217K |
| 代理商： | IMC064FLSG |
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E
iMC008/016/024/032/048/064FLSG
9
PRELIMINARY
Table 2. 5 Volt Value Series 200 Flash Memory PC Card Interface Signal Description
(Continued)
Symbol
Type
Name and Function
WP
OUTPUT
WRITE PROTECT:
This signal is pulled LOW for PC Card Standard
compatibility. The flash memory card has no WP signal functionality.
V
PP1
,V
PP2
N.C.
PROGRAM/ERASE POWER SUPPLY:
These power signals are not
connected on the card as the card’s memory devices use V
CC
for program
(write) and erase power.
V
CC
GND
CARD POWER SUPPLY:
5.0 V for all internal circuitry.
GROUND
for all internal circuitry.
REG#
INPUT
REGISTER SELECT:
The memory card has no separate attribute memory.
The CIS is located in common memory. REG# is unconnected on the card.
RST
INPUT
RESET:
Active high signal for placing card in Power-On Default State.
RESET can be used as a POWER-DOWN signal for the memory array.
WAIT#
OUTPUT
WAIT:
(Extended Bus Cycle) This signal is pulled high for PC Card Standard
compatibility. The flash memory card has no WAIT# signal functionality.
BVD
1
,
BVD
2
VS
1
, VS
2
OUTPUT
BATTERY VOLTAGE DETECT:
These signals are pulled high to maintain
SRAM card compatibility.
OUTPUT
VOLTAGE SENSE:
Notifies the host socket of the card’s V
CC
requirements.
VS
1
and VS
2
are OPEN to indicate a 5 V V
CC
card has been inserted.
RESERVED FOR FUTURE USE
RFU
N.C.
NO INTERNAL CONNECTION TO CARD
pin may be driven or left floating.
4.0
MEMORY CONTROL LOGIC
4.1
Bus Operations
The host executes memory read, write and erase
operations by issuing the appropriate command to
the Flash memory’s Command User Interface
(CUI). The CUI, which supports the command set of
the card’s memory devices, serves as the interface
between the host processor and internal operation
of a flash device. Commands can be issued to the
CUI using standard microprocessor bus cycles.
Table 3 lists the PC Card’s bus operations and
modes. For each listed bus operation or mode the
table defines the value of the card’s relevant bus
and control signals.
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