參數(shù)資料
型號： IMC064FLSG
廠商： INTEL CORP
元件分類： DRAM
英文描述： 5 V Series 200 Flash Memory Card(5V系列200閃速存儲器插卡)
中文描述： 64M X 8 FLASH 5V PROM CARD, 200 ns, XMA68
封裝： PC CARD
文件頁數(shù)： 18/35頁
文件大小： 217K
代理商： IMC064FLSG
iMC008/016/024/032/048/064FLSG
E
18
PRELIMINARY
5.1.7
WORD-WRITE COMMAND
Word-write commands are executed in a two-cycle
command sequence. Word-write command setup
(standard 40H or alternate 10H) is written in the first
cycle and then followed in the next cycle by a
second write that specifies the address and data
(latched on the rising edge of WE#) to be written in
memory. The WSM then takes over, controlling the
word-write
and
word-write
internally. After the word-write command sequence
is written, the device automatically outputs status
register data when read. The CPU can detect the
completion of the write event by analyzing the logic
state of the BUSY# output or status register bit
SR.7.
verify
algorithms
When the word-write operation is complete, status
register bit SR.4 should be checked. If a write error
is detected, the status register should be cleared.
The internal WSM verify only detects errors for
“1”s
that do not successfully program to “0”s. The CUI
remains in read status register mode until it
receives another command.
Successful write operations require that the
corresponding block lock-bit be cleared. If a word
write
operation
is
corresponding block lock-bit is set, SR.1 and SR.4
will be set to “1.”
attempted
when
the
5.1.8
SET BLOCK LOCK-BIT COMMAND
A flexible block locking and unlocking scheme is
enabled via a combination of block lock-bits. The
block lock-bits gate memory write and erase
operations. Individual block lock-bits can be set
using the Set Block Lock-Bit command. Set Block
Lock-Bit commands are invalid while the WSM is
running or the device is suspended.
Set block lock-bit commands are executed by a
two-cycle sequence. The set block lock-bit setup
along with appropriate block or device address is
written followed by the set block lock-bit confirm
(and an address within the block to be locked). The
WSM then controls the set lock-bit algorithm. After
the sequence is written, the device automatically
outputs status register data when read. The CPU
can detect the completion of the set lock-bit event
by analyzing the logic state of the BUSY# pin
output or status register bit SR.7.
When the set lock-bit operation is complete, status
register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The
CUI will remain in read status register mode until a
new command is issued.
This two-step sequence of set-up followed by
execution ensures that lock-bits are not accidentally
set. An invalid Set Block Lock-Bit command will
result in status register bits SR.4 and SR.5 being
set to “1.”
5.1.9
CLEAR BLOCK LOCK-BITS
COMMAND
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. This command is
invalid while the WSM is running or the device is
suspended.
Clear block lock-bits command is executed by a
two-cycle sequence. A clear block lock-bits setup is
first written followed by the clear block lock-bits
confirm. The device automatically outputs status
register data when read. The CPU can detect
completion of the clear block lock-bits event by
analyzing the logic state of the BUSY# pin output or
status register bit SR.7.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bit
error is detected, the status register should be
cleared. The CUI will remain in read status register
mode until another command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-
Bits command sequence will result in status register
bits SR.4 and SR.5 being set to “1.”
If a clear block lock-bits operation is aborted due to
V
CC
transitioning out of valid range or RESET#
active transition, block lock-bit values are left in an
undetermined state. A repeat of the Clear Block
Lock-Bits command is then required to initialize
block lock-bit contents to known values.
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