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參數(shù)資料
| 型號(hào)： | IMC032FLSG |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5 V Series 200 Flash Memory Card(5V系列200閃速存儲(chǔ)器插卡) |
| 中文描述： | 32M X 8 FLASH 5V PROM CARD, 200 ns, XMA68 |
| 封裝： | PC CARD |
| 文件頁數(shù)： | 8/35頁 |
| 文件大?。?/td> | 217K |
| 代理商： | IMC032FLSG |
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iMC008/016/024/032/048/064FLSG
E
8
PRELIMINARY
Table 1. 5 Volt Value Series 200 Flash Memory PC Card Definitions
(Continued)
Pin
Signal
I/O
Function
Active
Pin
Signal
I/O
Function
Active
53
A
22
I
Address Bit 22
61
REG#
I
Attribute
Memory Select
54
A2
3
I
Address Bit 23
62
BVD
2
O
Battery Voltage
Detect 2
55
A
24
I
Address Bit 24
63
BVD
1
O
Battery Voltage
Detect 1
56
A
25
I
Address Bit 25
N.C.
64
DQ
8
I/O Data Bit 8
57
VS
2
O
Voltage Sense 2
N.C.
65
DQ
9
I/O Data Bit 9
58
RST
I
Reset
HIGH
66
DQ
10
I/O Data Bit 10
59
WAIT#
O
Extend Bus
Cycle
LOW
67
CD
2
#
O
Card Detect 2
LOW
60
RFU
Reserved
68
GND
Ground
Table 2. 5 Volt Value Series 200 Flash Memory PC Card Interface Signal Description
Symbol
Type
Name and Function
A
0
–A
25
INPUT
ADDRESS INPUTS:
A
0
through A
25
enable direct addressing of up to 64 MB
of memory on the card. Signal A
0
is not decoded since the card is x16 only.
The memory will wrap at the card density boundary. The system should
not
try to access memory beyond the card’s density, since the upper addresses
are not decoded.
DQ
0
–DQ
15
INPUT/
OUTPUT
DATA INPUT/OUTPUT:
DQ
0
through DQ
15
constitute the bi-directional data
bus. DQ
15
is the most significant bit.
CARD ENABLE 1 & 2:
CE
1
# enables accesses on the low byte of the data
bus D
0
–7
. CE
2
# enables accesses on the high byte of the data bus D
8–15
. Both
CE
1
# and CE
2
# are active low signals. A host is expected to assert both CE
1
#
and CE
2
# as the card’s memory provides for word-wide data transfers but not
byte-wide data transfers.
CE
1
#, CE
2
#
INPUT
OE#
INPUT
OUTPUT ENABLE:
Active low signal enabling read data from the memory
card.
WE#
INPUT
WRITE ENABLE:
Active low signal gating write data to the memory card.
RDY/BSY#
OUTPUT
READY/BUSY OUTPUT:
Indicates status of internally timed erase or write
activities. A high output indicates the memory card is ready to accept
accesses.
CD
1
#,
CD
2
#
OUTPUT
CARD DETECT 1 & 2:
These signals provide for card insertion detection. The
signals are connected to ground internally on the memory card, and will be
forced low whenever a card is placed in the socket. The host socket interface
circuitry shall supply 10K or larger pull-up resistors on these signal pins.
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