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參數(shù)資料
| 型號： | IMC032FLSG |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5 V Series 200 Flash Memory Card(5V系列200閃速存儲器插卡) |
| 中文描述： | 32M X 8 FLASH 5V PROM CARD, 200 ns, XMA68 |
| 封裝： | PC CARD |
| 文件頁數(shù)： | 13/35頁 |
| 文件大?。?/td> | 217K |
| 代理商： | IMC032FLSG |
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E
5.0
iMC008/016/024/032/048/064FLSG
13
PRELIMINARY
COMMAND DEFINITION
The operations of the card’s memory device(s) are
selected by the writing of specific commands into
the CUI. The 5 Volt Value Series 200 Flash
Memory PC Card implements two command sets:
the basic command set and the scaleable
command set. The Basic Command Set is
backward compatible with Value Series 100 Flash
Memory PC Card with the exception that write
(program) suspend is not supported in the Series
200. The Scaleable Command Set adds three
capabilities to the PC Card in addition to the Basic
Command Set:
1.
2.
Common Flash Interface (CFI);
buffered writes which employ a 32-byte write
buffer to allow higher performance writes than
available with the Basic Command Set; and
a configurable BUSY# output.
3.
5.1
Basic Command Set
Table 4 presents the 5 Volt Value Series 200 PC
Card’s Basic Command Set. The table indicates
that the commands require one or more bus cycles
to implement. The table and notes following the
table
describe
each
descriptions of the individual commands follow in
subsections of the current document section.
bus
cycle.
Complete
5.1.1
READ ARRAY COMMAND
Upon initial device power-up and after exit from
reset/power-down mode, the card’s
devices default to read array mode. This operation
is also initiated by writing the Read Array command
to a memory device. The device remains enabled
for reads until another command is written. Once
the internal WSM has started a block erase, write,
or lock-bit configuration, the device will not
recognize the Read Array command until the WSM
completes its operation unless the WSM is
suspended via an Erase Suspend command.
memory
Table 4. Basic Command Set Definitions
(9)
Command
Bus
Cycles
Req’d.
Notes
First Bus Cycle
Second Bus Cycle
Oper
(1)
Addr
(2)
Data
(3,4)
Oper
(1)
Addr
(2)
Data
(3,4)
Read Array
1
Write
X
XXFFH
Read Identifier Codes
≥
2
5
Write
X
XX90H
Read
IA
ID
Read Status Register
2
Write
X
XX70H
Read
X
SRD
Clear Status Register
1
Write
X
XX50H
Word Write
2
6, 7
Write
X
XX40H
or
XX10H
Write
WA
WD
Block Erase
2
7
Write
X
XX20H
Write
BA
XXD0H
Block Erase Suspend
1
7
Write
X
XXB0H
Block Erase Resume
1
7
Write
X
XXD0H
Set Block Lock-Bit
2
Write
X
XX60H
Write
BA
XX01H
Clear Block Lock-Bits
2
8
Write
X
XX60H
Write
X
XXD0H
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