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參數(shù)資料
| 型號(hào)： | iMC020FLSA |
| 廠商： | Intel Corp. |
| 英文描述： | 5 Volt Series 2 Flash Memory Card(5V系列2閃速存儲(chǔ)器卡) |
| 中文描述： | 5伏2系列閃存卡（5V的系列2閃速存儲(chǔ)器卡） |
| 文件頁(yè)數(shù)： | 26/51頁(yè) |
| 文件大?。?/td> | 827K |
| 代理商： | IMC020FLSA |
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iMC002/004/010/020FLSA
E
26
PRELIMINARY
Start
Issue Write Setup
(1)
Command
Write Data
Read Status Register
(2)
Done
Writing Data
Full Status
(3)
Check if Desired
Write Operation
(4)
Completed
FULL STATUS CHECK PROCEDURE
Yes
No
Read Status Register
Data (See Above)
Voltage Range Error
(5)
Data Write Error
(6)
V
PP
Level OK
Data Write OK
No
Yes
No
Yes
Bus
Operation
Write
x8 Mode
Data to Be Written
Address = Byte
Within Card to Be
Written
x16 Mode
Write
Data = 40H
Address = Byte
Within Card to Be
Written
Data = 4040H
Address = Word
Within Card to Be
Written
Data to Be Written
Address = Word
Within Card to Be
Written
Read
Status Register
Data. Toggle OE#,
CE
# or CE
# to
Update Status
Register
Status Register
Data. Toggle OE#,
(CE
# or CE
2
#) to
Update Status
Registers
Check SR Bits
7 and 15
1 = Ready
2 = Busy
Standby
Check SR Bit 7
1 = Ready
2 = Busy
Data Write Successful
Bus
Operation
Standby
x8 Mode
x16 Mode
Check SR Bits
4 and 12
1 = Data Write Error
Standby
Check SR Bit 4
1 = Data Write Error
Check SR Bit 3
1 = V
PP
Detected
Low
Check SR Bits
3 and 11
1 = V
PP
Detected
Low
Command
Data Write
Write Setup
Defaults to
Device Status
Register Read
Mode
Command
FIG13
NOTES:
1.
2.
3.
4.
5.
Repeat for subsequent data writes.
In addition, the card’s ready-busy status register or the RDY/BSY# pin may be used.
Full device-level status check can be done after each data write or after a sequence of data writes.
Write FFH (or FFFFH) after the last data write operation to reset the device(s) to read array mode.
If a data write operation fails due to a low V
(setting SR Bit 3), the Clear Status Register command
must
be issued
before further attempts are allowed by the Write State Machine.
If a data write operation fails during a multiple write sequence, SR Bit 4 (Write Status) will not be cleared until the
Command User Interface receives the Clear Status Register command.
6.
Figure 13. Device-Level Automated Write Algorithm
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