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參數(shù)資料
| 型號： | IMC016FLSC |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5 V Value Series 100 Flash Memory Card(5V 100系列閃速存儲(chǔ)器卡) |
| 中文描述： | 8M X 16 FLASH 5V PROM CARD, 100 ns, XMA68 |
| 封裝： | PC CARD-68 |
| 文件頁數(shù)： | 19/29頁 |
| 文件大小： | 211K |
| 代理商： | IMC016FLSC |
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E
7.0
iMC002/004/008/016FLSC
19
PRELIMINARY
SYSTEM DESIGN
CONSIDERATIONS
7.1
Power Supply Decoupling
Flash memory power-switching characteristics
require
careful
device
designers are interested in three supply current
issues: standby, active and transient current peaks
which are produced by rising and falling edges of
CE
# and CE
#. The capacitive and inductive loads
on the card and internal flash memory device pairs
determine the magnitudes of these peaks.
decoupling.
System
Three-line control and proper decoupling capacitor
selection suppress transient voltage peaks. The
Value Series 100 cards contain on-card ceramic
decoupling capacitors connected between V
CC
and
GND.
The card connector should also have a 4.7 μF
electrolytic capacitor between V
and GND. The
bulk capacitors overcome voltage slumps caused
by printed-circuit-board trace inductance, and
supply charge to the smaller capacitors as needed.
7.2
Power-Up/Down Protection
The PCMCIA/JEIDA-specified socket properly
sequences the power supplies to the flash memory
card via shorter and longer pins.
Each device in the memory card is designed to
offer protection against accidental erasure or
writing, caused by spurious system-level signals
that may exist during power transitions. The card
will power-up into the read state.
A system designer must guard against active writes
for V
voltages above V
(2.0 V). Since both
WE# and CE
# must be low for a command write,
driving either to V
will inhibit writes. With its
control register architecture, alteration of device
contents only occurs after successful completion of
the two-step command sequences.
7.3
RDY/BSY# and Program/Block
Erase Polling
RDY/BSY# is a full CMOS output that provides a
hardware method of detecting program and block
erase completion. It transitions low time t
after
a Program or Erase command sequence is written
to a 28F0XXS5, and returns to V
when all the
WSM has finished executing the internal algorithm.
RDY/BSY# can be connected to the interrupt input
of the system CPU or controller. It is active at all
times. RDY/BSY# is also V
when the device is in
erase suspend or deep power-down modes.
7.4
V
CC
, V
PP
, RESET Transitions
and the Command/Status
Registers
Program and block erase completion are not
guaranteed if the internally generated V
drops
below V
. If the V
Status bit of the status
register (SR.3) is set to “1,” a Clear Status Register
command
must
be
program/block erase attempts are allowed by the
WSM. Otherwise, the Program (SR.4) or Erase
Status (SR.5) bits of the status register will be set
to “1”s, if error is detected. RESET transitions to V
IH
during program and block erase also abort the
operations. Data is partially altered in either case,
and the command sequence must be repeated after
normal operation is restored. Device power-off, or
RESET transitions to V
, clear the status register
to initial value 10000XXX for the upper eight bits.
issued
before
further
The CUI latches commands, as issued by system
software, and is not altered by CE# transitions, or
WSM actions. Its state upon power-up, after exit
from deep power-down or after V
CC
transitions
below V
LKO
, is read array mode.
After program or block erase is complete, the CUI
must be reset to read array mode via the Read
Array command, if access to the memory array is
desired.
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