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參數(shù)資料
| 型號(hào)： | IMC004FLSC |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5 V Value Series 100 Flash Memory Card(5V 100系列閃速存儲(chǔ)器卡) |
| 中文描述： | 2M X 16 FLASH 5V PROM CARD, 100 ns, XMA68 |
| 封裝： | PC CARD-68 |
| 文件頁數(shù)： | 9/29頁 |
| 文件大?。?/td> | 211K |
| 代理商： | IMC004FLSC |
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E
iMC002/004/008/016FLSC
9
PRELIMINARY
Table 2. Value Series 100 Card Signal Description
Symbol
Type
Name and Function
A
0
–A
25
INPUT
ADDRESS INPUTS:
A
0
through A
25
enable direct addressing of up to 64 MB
of memory on the card. Signal A
0
is not decoded since the card is x16 only.
The memory will wrap at the card density boundary. The system should NOT
try to access memory beyond the card’s density, since the upper addresses
are not decoded.
DQ
0
–DQ
15
INPUT/
OUTPUT
DATA INPUT/OUTPUT:
DQ
0
through DQ
15
constitute the bi-directional data
bus. DQ
15
is the most significant bit.
CARD ENABLE 1 & 2:
CE
1
# enables EVEN byte accesses on D
0
–7
, CE
2
#
enables ODD byte accesses on D
8–15
. Cannot access Odd Bytes on D
0–7
.
CE
1
#, CE
2
#
INPUT
OE#
INPUT
OUTPUT ENABLE:
Active low signal enabling read data from the memory
card.
WE#
INPUT
WRITE ENABLE:
Active low signal gating write data to the memory card.
RDY/BSY#
OUTPUT
READY/BUSY OUTPUT:
Indicates status of internally timed erase or program
activities. A high output indicates the memory card is ready to accept
accesses.
CD
1
#,
CD
2
#
OUTPUT
CARD DETECT 1 & 2:
These signals provide for card insertion detection. The
signals are connected to ground internally on the memory card, and will be
forced low whenever a card is placed in the socket. The host socket interface
circuitry shall supply 10K or larger pull-up resistors on these signal pins.
WP
OUTPUT
WRITE PROTECT:
This signal is pulled LOW for PC Card Standard
compatibility. The flash memory card has no WP signal functionality.
V
PP1
,V
PP2
N.C.
PROGRAM/ERASE POWER SUPPLY:
These power signals are not
connected for the 5 V-only card.
V
CC
GND
CARD POWER SUPPLY:
5.0 V for all internal circuitry.
GROUND
for all internal circuitry.
REG#
INPUT
REGISTER SELECT:
The memory card has no separate attribute memory.
The CIS is located in common memory. REG# is unconnected on the card.
RST
INPUT
RESET:
Active high signal for placing card in Power-On Default State.
RESET can be used as a POWER-DOWN signal for the memory array.
WAIT#
OUTPUT
WAIT:
(Extended Bus Cycle) This signal is pulled high for compatibility.
BVD
1
,
BVD
2
VS
1
, VS
2
OUTPUT
BATTERY VOLTAGE DETECT:
These signals are pulled high to maintain
SRAM card compatibility.
OUTPUT
VOLTAGE SENSE:
Notifies the host socket of the card’s V
CC
requirements.
VS
1
and VS
2
are OPEN to indicate a 5 V, 16-bit card has been inserted.
RESERVED FOR FUTURE USE
RFU
N.C.
NO INTERNAL CONNECTION TO CARD
pin may be driven or left floating.
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