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參數(shù)資料
| 型號： | IL1815N |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | AMPLIFIER IC FOR SENSORS WITH DIFFERENT CONDUCTANCE |
| 中文描述： | 放大器IC與不同電導傳感器 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 195K |
| 代理商： | IL1815N |
IL1815
7
Mode 3, output 05 - grounded.
With grounded output 05, input switching threshold is set from 0 V (typical rate) up to
±
25 mV
(maximum). Positive wave (front) of input signal crossing zero equip the zero detector and the
next coming negative wave (edge) - start the IC. This is the main IC application mode.
Single-ended operation synchronization.
Pulse synchronization is preset by resistor and capacitor connected to output 14. Preferred
maximum resistor value - 150 kOhm. Capacitance may be changed if needed (according to
application requirements), until capacitor variable is not showing any leakage which will result
adversely in RC - constant variable.
Width of input pulse is determined by formula:
W = 0.673 x R x C
Since normally generated is a string of pulses of a determined width, preferred maximum input
signal frequency is:
F
I
(maximum) = 1 / (1.346 x R x C)
(3)
In an applied example shown in figure 1 (R=150 kOhm, C=0.001 mkF), preferred maximum
input frequency will usually be 5 kHz. Under influence of input frequency higher than preferred F
I
(maximum) value, operation of electrical circuit may be unreliable. For the applications which do
not require generation of pulses into electrical circuit (i.e. in static operation mode), output 14 may
be directly connected to the ground.
Logic inputs and outputs.
In some systems it’s necessary to generate pulses, for example, under conditions of engine
shutdown (when motor car is stopped), when variable reactive sensor has no output signal.
External input pulses from output 09 strobed (pulses controlled) from choice input (output 11), go
to output 10 when there is a high level (H) on output 11. Output 12 - a direct output of data
(generated pulses), is not subject to influence of logic on output 11.
Input/output pins 09, 11, 10 and 12 are compatible with CMOS logic. Besides, pins 09, 11 and
12 are compatible with TTL logic. Output 10 is not meant for controlling TTL loading (see fig.3).
Output 12 - an open collector of NPN-transistor.
Pins 01, 04, 06 and 13 do not have internal connections and may be grounded.
(2)
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