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參數(shù)資料
| 型號(hào)： | IFM008A |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 3/5 Volt Series 100 Flash Memory Miniature Card(3/5V 100系列閃速存儲(chǔ)器微型卡) |
| 中文描述： | 8M X 8 FLASH 3V PROM CARD, 100 ns, XMA60 |
| 文件頁(yè)數(shù)： | 9/31頁(yè) |
| 文件大小： | 258K |
| 代理商： | IFM008A |
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E
4.1.4
iFM002/004/008A
9
PRELIMINARY
DEEP POWER-DOWN
RESET# at V
IL
initiates the deep power-down
mode.
During reads, an active RESET# deselects the
memory, places output drivers in a high-impedance
state, and turns off all internal circuits. RESET#
must be held low for a minimum of 100 ns. After
returning from deep power-down, the host must
wait before initial memory access outputs are valid,
as determined by t
PHQV
. After this wake-up interval,
the host can resume normal operations to the card.
Card reset forces the CUI to reset to read array
mode and sets the status register to 80H.
During block erase, byte write, or lock-bit
configuration modes, an active RESET# will abort
the operation. BUSY# remains low until the reset
operation completes. Memory contents being
altered are no longer valid; the data may be partially
erased or written. The host must wait after RESET#
goes to logic-high (V
) before it can write another
command, as determined by t
PHWL
.
It is important to assert RESET# to the card during
a system reset. When a host comes out of reset, it
may require the ability to immediately execute code
from the card. If a CPU reset occurs without a card
reset, the host will not be able to read from the card
if that card is in a different mode when the system
reset occurs. For example, if an end-user initiates a
host reset when the card is in read status register
mode, the host will attempt to read code from the
card, but will actually read status register data.
Intel’s Series 100 Miniature Card allows proper card
reset following a system reset through the use of
the RESET# input. System RESET# circuitry can
reset the host CPU in addition to the card.
4.1.5
READ IDENTIFIER CODES
OPERATION
The read identifier codes operation outputs the
manufacturer code, device code, and block lock
configuration codes (for each block), see Figure 3.
Using the manufacturer and device codes, the
system CPU can automatically match the device
with its proper algorithms. The block lock codes
identify locked and unlocked blocks.
(Blocks 2 through 14)
Block 15 Lock Configuration Code
Block 1 Lock Configuration Code
Manufacturer Code
Device Code
Block 0 Lock Configuration Code
Reserved for Future
Implementation
Reserved for Future
Implementation
Reserved for Future
Implementation
Reserved for Future
Implementation
Reserved for Future
Implementation
Block 15
Block 1
Block 0
FFFFF
F0004
F0003
F0002
F0001
F0000
1FFFF
10004
10003
10002
10001
10000
0FFFF
00004
00003
00002
00001
00000
0581_03
Figure 3. Device Identifier Code Memory Map
4.1.6
CUI WRITES
Writes to the CUI enable reading of device data and
intelligent identifiers. They also control inspection
and clearing of the status register. The contents of
the interface register serves as input to the internal
state machine on each component.
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