1272
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
47.19 Two-wire Interface Characteristics
Table 47-47 describes the requirements for devices connected to the Two-wire Serial Bus.
Notes: 1. Required only for fTWCK > 100 kHz.
2. Cb = capacitance of one bus line in pF. Per I2C Standard, Cb Max = 400 pF
3. The TWCK low period is defined as follows: tlow = ((CLDIV × 2
CKDIV) + 4) × tMCK
4. The TWCK high period is defined as follows: thigh = ((CHDIV × 2CKDIV) + 4 × tMCK
5. tCP_MCK = MCK bus period.
Table 47-47. Two-wire Serial Bus Requirements
Symbol
Parameter
Conditions
Min
Max
Unit
VIL
Input Low-voltage
—
-0.3
0.3
× VDDIO
V
VIH
Input High-voltage
—
0.7
× VDDIO
VCC + 0.3
V
VHYS
Hysteresis of Schmitt Trigger Inputs
—
0.150
–
V
VOL
Output Low-voltage
3 mA sink current
—
0.4
V
tR
Rise Time for both TWD and TWCK
20 + 0.1Cb
300
ns
tOF
Output Fall Time from VIHmin to VILmax
10 pF < Cb < 400 pF
250
ns
Capacitance for each I/O Pin
—
10
pF
fTWCK
TWCK Clock Frequency
—
0
400
kHz
Rp
Value of Pull-up Resistor
fTWCK ≤ 100 kHz
(VDDIO - 0.4V) ÷ 3mA
1000ns
÷ Cb
Ω
fTWCK > 100 kHz
(VDDIO - 0.4V) ÷ 3mA
300ns
÷ Cb
Ω
tLOW
Low Period of the TWCK Clock
fTWCK ≤ 100 kHz
—
s
fTWCK > 100 kHz
—
s
tHIGH
High Period of the TWCK Clock
fTWCK ≤ 100 kHz
—
s
fTWCK > 100 kHz
—
s
tHD;STA
Hold Time (repeated) START condition
fTWCK ≤ 100 kHz
tHIGH
—
s
fTWCK > 100 kHz
tHIGH
—
s
tSU;STA
Set-up Time for a Repeated START
condition
fTWCK ≤ 100 kHz
tHIGH
—
s
fTWCK > 100 kHz
tHIGH
—
s
tHD;DAT
Data Hold Time
fTWCK ≤ 100 kHz
0
3
s
fTWCK > 100 kHz
0
3
s
tSU;DAT
Data Setup Time
fTWCK ≤ 100 kHz
—ns
fTWCK > 100 kHz
—ns
tSU;STO
Setup Time for STOP condition
fTWCK ≤ 100 kHz
tHIGH
—
s
fTWCK > 100 kHz
tHIGH
—
s
tHD;STA
Bus free time between a STOP and START
condition
fTWCK ≤ 100 kHz
tHIGH
—
s
fTWCK > 100 kHz
tHIGH
—
s