![](http://datasheet.mmic.net.cn/100000/ID80C32E-L16SHXXX_datasheet_3493627/ID80C32E-L16SHXXX_1133.png)
1133
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
46.7.14 LCD Controller Interrupt Status Register
Name:
LCDC_LCDISR
Address:
0xF8038038
Access:
Read-only
Reset:
0x00000000
SOF: Start of Frame Interrupt Status Register
When set to one, this flag indicates that a start of frame event has been detected. This flag is reset after a read operation.
DIS: LCD Disable Interrupt Status Register
When set to one, this flag indicates that the horizontal and vertical timing generator has been successfully disabled. This flag is
reset after a read operation.
DISP: Power-up/Power-down Sequence Terminated Interrupt Status Register
When set to one, this flag indicates whether the power-up sequence or power-down sequence has terminated. This flag is reset
after a read operation.
FIFOERR: Output FIFO Error
When set to one, this flag indicates that an underflow occurs in the output FIFO. This flag is reset after a read operation.
BASE: Base Layer Raw Interrupt Status Register
When set to one, this flag indicates that a Base layer interrupt is pending. This flag is reset as soon as the BASEISR register is
read.
OVR1: Overlay 1 Raw Interrupt Status Register
When set to one, this flag indicates that an Overlay 1 layer interrupt is pending. This flag is reset as soon as the OVR1ISR register
is read.
HEO: High End Overlay Raw Interrupt Status Register
When set to one, this flag indicates that a Hi End layer interrupt is pending. This flag is reset as soon as the HEOISR register is
read.
HCR: Hardware Cursor Raw Interrupt Status Register
When set to one, this flag indicates that a Hardware Cursor layer interrupt is pending. This flag is reset as soon as the HCRISR
register is read.
31
30
29
28
27
26
25
24
–
–––––––
23
22
21
20
19
18
17
16
–
–––––––
15
14
13
12
11
10
9
8
–
HCR
HEO
OVR1
BASE
7
6543210
–
FIFOERR
–
DISP
DIS
SOF