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1119
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
46.7.1 LCD Controller Configuration Register 0
Name:
LCDC_LCDCFG0
Address:
0xF8038000
Access:
Read-write
Reset:
0x00000000
CLKPOL: LCD Controller Clock Polarity
0: Data/Control signals are launched on the rising edge of the Pixel Clock.
1: Data/Control signals are launched on the falling edge of the Pixel Clock.
CLKSEL: LCD Controller Clock Source Selection
0: The Asynchronous output stage of the LCD controller is fed by MCK.
1: The Asynchronous output state of the LCD controller is fed by 2x MCK.
CLKPWMSEL: LCD Controller PWM Clock Source Selection
0: The slow clock is selected and feeds the PWM module.
1: The system clock is selected and feeds the PWM module.
CGDISBASE: Clock Gating Disable Control for the Base Layer
0: Automatic Clock Gating is enabled for the Base Layer.
1: Clock is running continuously.
CGDISOVR1: Clock Gating Disable Control for the Overlay 1 Layer
0: Automatic Clock Gating is enabled for the Overlay 1 Layer.
1: Clock is running continuously.
CGDISHEO: Clock Gating Disable Control for the High End Overlay
0: Automatic Clock Gating is enabled for the High End Overlay Layer.
1: Clock is running continuously.
CGDISHCR: Clock Gating Disable Control for the Hardware Cursor Layer
0: Automatic Clock Gating is enabled for the Hardware Cursor Layer.
1: Clock is running continuously.
CLKDIV: LCD Controller Clock Divider
8 bit width clock divider for pixel clock LCD_PCLK.
pixel_clock = selected_clock/(CLKDIV+2)
Where selected_clock is equal to system_clock when CLKSEL field is set to 0 and system_clock2x when CLKSEL is set to one.
31
30
29
28
27
26
25
24
–
–––––––
23
22
21
20
19
18
17
16
CLKDIV
15
14
13
12
11
10
9
8
–
CGDISHCR
CGDISHEO
–
CGDISOVR1
CGDISBASE
7
6543210
–
CLKPWMSEL
CLKSEL
–
CLKPOL