參數(shù)資料
型號: IDTCV110JP
廠商: Integrated Device Technology, Inc.
英文描述: PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
中文描述: 可編程FLEXPC時鐘P4處理器
文件頁數(shù): 5/16頁
文件大小: 76K
代理商: IDTCV110JP
COMMERCIAL TEMPERATURE RANGE
IDTCV110J
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
5
CONTROL REGISTERS
N PROGRAMMING PROCEDURE
Use Index byte write.
For N programmng, the user only needs to access Byte17, Byte 25, and Byte8.
1.
2.
3.
Write Byte17 for CPU PLL N, CPU f = N*Resolution, see resolution table below Byte17.
Write Byte25 for SRC PLL N, SRC f = N*0.666667, PCI = SRC f /3, SATA f = SRC f.
Enable N Programmng bit, Byte8 bit1. Once this bit is enabled, any N value will be changed on the fly.
Center spread only works when the N Programmng bit is enabled. Down spread is OK even N Programmng bit is disabled
It is OK to change N value to any value on the bench test board. In the system IDT recommends the stepping change. It is unknown how much
the systemcan sustain for each stepping change; the estimate is about 5. If the N changes too much in one step, the systemwill likely hang.
Note that SATA is with SRC PLL. This SATA Hard Drive mght not operate during SRC N programmng.
Most of the Bytes, fromByte8-Byte31, are used to adjust output waveforms and SSC modulation profiles. The power on setting will be changed according
to each power on frequency selection. To avoid mstakes, dont write on those byte (be careful about Block Write). It is suggested to use the Index Byte
write to access bytes.
SSC MAGNITUDE CONTROL, SMC
SMC[2:0]
000
001
010
011
100
101
110
111
-0.25
-0.5
-0.75
-1
±0.125
±0.25
±0.375
±0.5
FS_C, B, A
101
001
011
010
000
100
110
111
CPU
100
133
166
200
266
333
400
RESERVE
FREQUENCY SELECTION TABLE
RESOLUTION
CPU (MHz)
100
133
166
200
266
333
400
Resolution
0.666667
0.666667
1.333333
1.333333
1.333333
2.666667
2.666667
N =
150
200
125
150
200
125
150
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