參數(shù)資料
型號(hào): IDTCV110JP
廠商: Integrated Device Technology, Inc.
英文描述: PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
中文描述: 可編程FLEXPC時(shí)鐘P4處理器
文件頁數(shù): 3/16頁
文件大?。?/td> 76K
代理商: IDTCV110JP
COMMERCIAL TEMPERATURE RANGE
IDTCV110J
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
3
PIN DESCRIPTION
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Name
V
DD
_PCI
V
SS
_PCI
PCI3
PCI4
PCI5
V
SS
_PCI
V
DD
_PCI
PCIF0/ITP_EN
PCIF1
PCIF2
V
DD
48
USB48
V
SS
48
DOT96
DOT96#
FSB/TEST_MODE
V
TT
_P
WRGD
#/PD
Type
PWR
GND
OUT
OUT
OUT
GND
PWR
I/O
OUT
OUT
PWR
OUT
GND
OUT
OUT
IN
IN
Description
3.3V
GND
PCI clock
PCI clock
PCI clock
GND
3.3V
PCI clock, free running. CPU2 select (sampled on V
TT
_P
WRGD
# assertion) HIGH = CPU2.
PCI clock, free running
PCI clock, free running
3.3V
48MHz clock
GND
96MHz 0.7 current mode differential clock output
96MHz 0.7 current mode differential clock output
CPU frequency selection. Selects R
EF
/N or Hi-Z when in test mode, Hi-Z = 1, R
EF
/N = 0.
Level-sensitive strobe used to latch the FSA, FSB, FSC/TEST_SEL, and PCIF0/ITP_EN inputs. After
V
TT
_P
WRGD
# assertion, becomes a real-time input for asserting power down. (Active HIGH)
CPU frequency selection
Differential serial reference clock
Differential serial reference clock
3.3V
Differential serial reference clock
Differential serial reference clock
Differential serial reference clock
Differential serial reference clock
Differential serial reference clock
Differential serial reference clock
3.3V
GND
Differential serial reference clock
Differential serial reference clock
Differential serial reference clock
Differential serial reference clock
3.3V
Selectable CPU or SRC differential clock output. ITP_EN = 0 at V
TT
_P
WRGD
#assertion = SRC7#
Selectable CPU or SRC differential clock output. ITP_EN = 0 at V
TT
_P
WRGD
# assertion = SRC7.
3.3V
GND
Reference current for differential output buffer
Host 0.7 current mode differential clock output
Host 0.7 current mode differential clock output
3.3V
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
FSA
SRC1
SRC1#
V
DD
_SRC
SRC2
SRC2#
SRC3
SRC3#
SRC4
SRC4#
V
DD
_SRC
V
SS
_SRC
SRC5#
SRC5
SRC6#
SRC6
V
DD
_SRC
IN
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
PWR
OUT
OUT
PWR
GND
OUT
OUT
OUT
PWR
CPU2_ITP#/SRC7#
CPU2_ITP/SRC7
V
DDA
V
SSA
I
REF
CPU1#
CPU1
V
DD
_CPU
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參數(shù)描述
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