參數(shù)資料
型號: IDTCV109E
廠商: Integrated Device Technology, Inc.
英文描述: CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
中文描述: 時鐘發(fā)生器的臺式機(jī)平臺
文件頁數(shù): 13/21頁
文件大小: 104K
代理商: IDTCV109E
COMMERCIAL TEMPERATURE RANGE
IDTCV109E
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
13
BY TE 32: WD SOFT RESET TIMER
WD Soft Alarmtimer has to be shorter than WD Hard Alarmtimer. WDE and WD Soft Alarmbits, Byte 33 bit 7 and bit 5, have to be enabled for this Soft Alarm
function.
Bit
Output(s) Affected
Description/Function
7
CPU WD Hard Alarm
0 = frequency select controlled by Byte 25 bit 7
safe frequency mode select
1 = CPU frequency specified
by WDBS[2:0] WDCFS[2:0]
6
WDCFS2
CPU WD time out safe frequency select
(1)
5
WDCFS1
4
WDCFS0
3
WD soft alarmtimer 3
Specify WD Soft AlarmTime Out time
2
WD soft alarmtimer 2
Time Out time = WD Soft AlarmTimer[3:0]*290ms
1
WD soft alarmtimer 1
Default is 580ms.
0
WD soft alarmtimer 0
0
1
Type
RW
Power On
0
HW/SMBus
WDBS
WDCFS
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
1
0
NOTE:
1. See SW FREQUENCY SELECTION table.
BY TE 33: WD CONTROL
Bit
7
6
Output(s) Affected
WDE
WD FS relatch
Description/Function
Watchdog enable
Relatch HW FS2, 1, 0
in event of WD Hard Alarmtime out
WD Soft Alarmenable
In event of WD Hard Alarmtime out
0
1
Type
RW
RW
Power On
0
0
Disable
Disable
Enable
Enable
5
4
WD Soft Alarmenable
AGP/PCI WD Hard Alarm
time out safe frequency mode select 0 = AGP/PCI frequency controlled by Byte 30 bit 6
1 = AGP/PCI frequency specified by WDAFS[2:0]
SRC SMC 2
SRC SMC 1
SRC SMC 0
Reserve
Disable
HW/SMBus
Enable
WDAFS
RW
RW
0
0
3
2
1
0
SRC SSC magnitude control
(1)
SRC SSC magnitude control
(1)
SRC SSC magnitude control
(1)
1
0
1
0
BY TE 34
Bit
7
Output(s) Affected
SW 24_48MHz control override
Description/Function
0
1
Type
RW
Power On
0
0 = controlled by hardware, 1 = controlled by bit 6 HW control controlled by
bit 6
24MHz
6
5
4
3
2
1
0
24_48MHz select
Reserve
48MHz
RW
RW
0
0
0
0
NOTE:
1. See SMC table.
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