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參數(shù)資料
| 型號(hào)： | IDT85304 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER |
| 中文描述： | 低偏移，1至5差分至3.3伏的LVPECL扇出緩沖器 |
| 文件頁(yè)數(shù)： | 8/11頁(yè) |
| 文件大?。?/td> | 77K |
| 代理商： | IDT85304 |
8
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE-ENDED LEVELS
The diagrambelow shows how the differential input can be wired to accept single-ended levels. The reference voltage V
REF
～
V
DD
/2 is generated by the
bias resistors R1, R2, and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 mght need to be adjusted to
position the V
REF
in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and V
DD
= 3.3V, V
REF
should be 1.25V and R2/
R1 = 0.609.
Single-Ended Signal Driving Differential Input
V
DD
V
REF
+
-
C1
0.1uF
CLK_IN
R1
1K
R2
1K
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termnation for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines.
F
OUT
and xF
OUT
are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, termnating resistors (DC current path to
ground) or current sources must be used for functionality. These outputs are designed to drive 50
transmssion lines. Matched impedance techniques should
be used to maximze operating frequency and mnimze signal distortion. The diagrams below show two different layouts which are recommended only as
guidelines. Other suitable clock layouts may exist. It is recommended that the board designers simulate to guarantee compatibility across all printed circuit and
clock component process variations.
LVPECL Output Termination, layout A
LVPECL Output Termination, layout B
F
OUT
50
50
Zo = 50
V
DD
- 2V
Zo = 50
R
TT
F
IN
R
TT
=
(V
OH
+ V
OL
/ V
DD
- 2) - 2
1
Zo
F
OUT
Zo = 50
Zo = 50
F
IN
Zo
3
2
Zo
3
2
Zo
5
2
Zo
5
2
3.3V
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| IDT85304-01 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER |
| IDT85304-01PGG | 功能描述:IC CLOCK BUFFER MUX 1:5 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:- 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| IDT85304-01PGG8 | 功能描述:IC CLOCK BUFFER MUX 1:5 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:- 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| IDT85304-01PGGI | 功能描述:IC CLOCK BUFFER MUX 1:5 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:- 產(chǎn)品培訓(xùn)模塊:High Bandwidth Product Overview 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:4 差分 - 輸入:輸出:是/是 輸入:CML，LVDS，LVPECL 輸出:CML 頻率 - 最大:2.5GHz 電源電壓:2.375 V ~ 2.625 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) |
| IDT85304-01PGGI8 | 功能描述:IC CLOCK BUFFER MUX 1:5 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:- 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
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