參數(shù)資料
型號： IDT82V3280DQ
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： WAN PLL
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： TQFP-100
文件頁數(shù)： 109/167頁
文件大?。?/td> 1039K
代理商： IDT82V3280DQ
IDT82V3280
WAN PLL
Programming Information
109
June 19, 2006
IN_FREQ_READ_STS - Input Clock Frequency Read Value
IN1_IN2_STS - Input Clock 1 & 2 Status
Address: 42H
Type: Read
Default Value: 00000000
Bit
Name
Description
7 - 0
IN_FREQ_VALUE[7:0]
These bits represent a 2’s complement signed integer. If the value is multiplied by the value in the
FREQ_MON_FACTOR[3:0] bits (b3~0, 2EH), the frequency of an input clock with respect to the reference clock in ppm will
be gotten. The input clock is selected by the IN_FREQ_READ_CH[3:0] bits (b3~0, 41H).
The value in these bits is updated every 16 seconds, starting when an input clock is selected.
Address: 43H
Type: Read
Default Value: X110X110
Bit
Name
Description
7
-
Reserved.
This bit indicates whether IN2 is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
This bit indicates whether IN2 is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
This bit indicates whether IN2 is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (
= TIME_OUT_VALUE[5:0] (b5~0, 08H) X
MULTI_FACTOR[1:0] (b7~6, 08H) in second
) which starts from when the alarm is raised.
Reserved.
This bit indicates whether IN1 is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
This bit indicates whether IN1 is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
This bit indicates whether IN1 is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (
= TIME_OUT_VALUE[5:0] (b5~0, 08H) X
MULTI_FACTOR[1:0] (b7~6, 08H) in second
) which starts from when the alarm is raised.
6
IN2_FREQ_HARD_ALARM
5
IN2_NO_ACTIVITY_ALARM
4
IN2_PH_LOCK_ALARM
3
-
2
IN1_FREQ_HARD_ALARM
1
IN1_NO_ACTIVITY_ALARM
0
IN1_PH_LOCK_ALARM
7
6
5
4
3
2
1
0
IN_FREQ_VAL
UE7
IN_FREQ_VAL
UE6
IN_FREQ_VAL
UE5
IN_FREQ_VAL
UE4
IN_FREQ_VAL
UE3
IN_FREQ_VAL
UE2
IN_FREQ_VAL
UE1
IN_FREQ_VAL
UE0
7
6
5
4
3
2
1
0
-
IN2_FREQ_HA
RD_ALARM
IN2_NO_ACTIV
ITY_ALARM
IN2_PH_LOCK
_ALARM
-
IN1_FREQ_HA
RD_ALARM
IN1_NO_ACTIV
ITY_ALARM
IN1_PH_LOCK
_ALARM
相關(guān)PDF資料
PDF描述
IDT82V3280DQG WAN PLL
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT82V3280DQG 功能描述:IC PLL WAN SE STRATUM 2 100-TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDT82V3280DQG8 功能描述:IC PLL WAN SE STRATUM 2 100-TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDT82V3280EQG 功能描述:IC PLL WAN SE STRATUM 2 100TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDT82V3280EQG8 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN SE STRATUM 2 100TQFP
IDT82V3280EQGBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
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