參數(shù)資料
型號(hào)： IDT82V3255DKG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： WAN PLL
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP64
封裝： GREEN, TQFP-64
文件頁數(shù)： 14/127頁
文件大?。?/td> 868K
代理商： IDT82V3255DKG
IDT82V3255
WAN PLL
Pin Description
14
June 19, 2006
IN3_CMOS
34
I
pull-down
CMOS
IN3_CMOS: Input Clock 3
A 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
Output Frame Synchronization Signal
FRSYNC_8K
17
O
CMOS
FRSYNC_8K: 8 kHz Frame Sync Output
An 8 kHz signal is output on this pin.
MFRSYNC_2K: 2 kHz Multiframe Sync Output
A 2 kHz signal is output on this pin.
MFRSYNC_2K
18
O
CMOS
Output Clock
OUT1_POS
OUT1_NEG
19
20
O
PECL/LVDS
OUT1_POS / OUT1_NEG: Positive / Negative Output Clock 1
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
4
, N x T1
5
, N x 13.0 MHz
6
, N x 3.84 MHz
7
,
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz clock is differentially output on this pair
of pins.
OUT2: Output Clock 2
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
4
, N x T1
5
, N x 13.0 MHz
6
, N x 3.84 MHz
7
,
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz or 155.52 MHz clock is output on this pin.
OUT2
56
O
CMOS
Microprocessor Interface
CS
44
I
pull-up
CMOS
CS
: Chip Selection
A transition from high to low must occur on this pin for each read or write operation and this
pin should remain low until the operation is over.
INT_REQ: Interrupt Request
This pin is used as an interrupt request. The output characteristics are determined by the
HZ_EN bit (b1, 0CH) and the INT_POL bit (b0, 0CH).
SDI: Serial Data Input
In Serial mode, this pin is used as the serial data input. Address and data on this pin are seri-
ally clocked into the device on the rising edge of SCLK.
INT_REQ
5
O
CMOS
SDI
CLKE
43
42
I
pull-down
CMOS
CLKE: SCLK Active Edge Selection
In Serial mode, this pin selects the active edge of SCLK to update the SDO:
High - The falling edge;
Low - The rising edge.
SDO: Serial Data Output
In Serial mode, this pin is used as the serial data output. Data on this pin is serially clocked
out of the device on the active edge of SCLK.
SCLK: Shift Clock
In Serial mode, a shift clock is input on this pin.
Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated
on the active edge of SCLK. The active edge is determined by the CLKE.
SDO
52
I/O
pull-down
CMOS
SCLK
47
I
pull-down
CMOS
JTAG (per IEEE 1149.1)
TRST
37
I
pull-down
CMOS
TRST
: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port.
This pin should be connected to ground when JTAG is not used.
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK.
TMS
41
I
pull-up
CMOS
Table 1: Pin Description (Continued)
Name
Pin No.
I/O
Type
Description
1
相關(guān)PDF資料
PDF描述
IDT82V3255TF WAN PLL
IDT82V3255TFG WAN PLL
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IDT82V3280DQG WAN PLL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT82V3255DKG8 功能描述:IC PLL WAN SMC STRATUM 3 64-TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDT82V3255EDGBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3255TF 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3255TFBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3255TFG 功能描述:IC PLL WAN SMC STRATUM 3 64-TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
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