參數(shù)資料
型號(hào)： IDT82V3255DK
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： WAN PLL
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP64
封裝： TQFP-64
文件頁(yè)數(shù)： 6/127頁(yè)
文件大?。?/td> 868K
代理商： IDT82V3255DK
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List of Tables
6
June 19, 2006
Table 1: Pin Description ............................................................................................................................................................................................. 13
Table 2: Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 17
Table 3: Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 18
Table 4: Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 19
Table 5: Related Bit / Register in Chapter 3.5 ........................................................................................................................................................... 21
Table 6: Input Clock Selection for T0 Path ................................................................................................................................................................ 22
Table 7: Input Clock Selection for T4 Path ................................................................................................................................................................ 22
Table 8: External Fast Selection ................................................................................................................................................................................ 22
Table 9: ‘n’ Assigned to the Input Clock ..................................................................................................................................................................... 23
Table 10: Related Bit / Register in Chapter 3.6 ........................................................................................................................................................... 23
Table 11: Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) .............................................................................. 24
Table 12: Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) .......................................................... 24
Table 13: Related Bit / Register in Chapter 3.7 ........................................................................................................................................................... 25
Table 14: Conditions of Qualified Input Clocks Available for T0 & T4 Selection ......................................................................................................... 26
Table 15: Related Bit / Register in Chapter 3.8 ........................................................................................................................................................... 27
Table 16: T0 DPLL Operating Mode Control ............................................................................................................................................................... 28
Table 17: T4 DPLL Operating Mode Control ............................................................................................................................................................... 30
Table 18: Related Bit / Register in Chapter 3.9 ........................................................................................................................................................... 30
Table 19: Frequency Offset Control in Temp-Holdover Mode ..................................................................................................................................... 31
Table 20: Frequency Offset Control in Holdover Mode ............................................................................................................................................... 32
Table 21: Holdover Frequency Offset Read ................................................................................................................................................................ 32
Table 22: Related Bit / Register in Chapter 3.10 ......................................................................................................................................................... 33
Table 23: Related Bit / Register in Chapter 3.11 ......................................................................................................................................................... 35
Table 24: Related Bit / Register in Chapter 3.12 ......................................................................................................................................................... 36
Table 25: Outputs on OUT1 & OUT2 if Derived from T0/T4 DPLL Outputs ................................................................................................................ 36
Table 26: Outputs on OUT1 & OUT2 if Derived from T0/T4 APLL .............................................................................................................................. 37
Table 27: Frame Sync Input Signal Selection .............................................................................................................................................................. 38
Table 28: Synchronization Control ............................................................................................................................................................................... 38
Table 29: Related Bit / Register in Chapter 3.13 ......................................................................................................................................................... 39
Table 30: Related Bit / Register in Chapter 3.14 ......................................................................................................................................................... 40
Table 31: Read Timing Characteristics in Serial Mode ................................................................................................................................................ 44
Table 32: Write Timing Characteristics in Serial Mode ................................................................................................................................................ 44
Table 33: JTAG Timing Characteristics ....................................................................................................................................................................... 45
Table 34: Register List and Map .................................................................................................................................................................................. 46
Table 35: Power Consumption and Maximum Junction Temperature ....................................................................................................................... 111
Table 36: Thermal Data ............................................................................................................................................................................................. 111
Table 37: Absolute Maximum Rating ......................................................................................................................................................................... 112
Table 38: Recommended Operation Conditions ........................................................................................................................................................ 112
Table 39: CMOS Input Port Electrical Characteristics ............................................................................................................................................... 113
Table 40: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics ................................................................................................ 113
Table 41: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ........................................................................................... 113
Table 42: CMOS Output Port Electrical Characteristics ............................................................................................................................................ 113
Table 43: PECL Input / Output Port Electrical Characteristics ................................................................................................................................... 115
Table 44: LVDS Input / Output Port Electrical Characteristics ................................................................................................................................... 116
Table 45: Output Clock Jitter Generation .................................................................................................................................................................. 117
Table 46: Output Clock Phase Noise ......................................................................................................................................................................... 118
Table 47: Input Jitter Tolerance (155.52 MHz) .......................................................................................................................................................... 118
Table 48: Input Jitter Tolerance (1.544 MHz) ............................................................................................................................................................ 118
List of Tables
相關(guān)PDF資料
PDF描述
IDT82V3255DKG WAN PLL
IDT82V3255TF WAN PLL
IDT82V3255TFG WAN PLL
IDT82V3280 WAN PLL
IDT82V3280DQ WAN PLL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT82V3255DKG 功能描述:IC PLL WAN SMC STRATUM 3 64-TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類(lèi)型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱(chēng):93786AFT
IDT82V3255DKG8 功能描述:IC PLL WAN SMC STRATUM 3 64-TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類(lèi)型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱(chēng):93786AFT
IDT82V3255EDGBLANK 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:WAN PLL
IDT82V3255TF 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:WAN PLL
IDT82V3255TFBLANK 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:WAN PLL
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