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參數(shù)資料
| 型號： | IDT82V2616BBG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 14/99頁 |
| 文件大小： | 0K |
| 描述： | IC INVERSE MUX 16CH ATM 272-PBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 無線 |
| 接口： | Utopia |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 封裝/外殼： | 260-BGA |
| 供應(yīng)商設(shè)備封裝： | 260-PBGA（19x19） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | 82V2616BBG |
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INTERFACE
21
December 4, 2006
IDT82V2616
Inverse Multiplexing for ATM
3.2.1.1 Mode0
In this mode, the transmit and receive data are viewed as a contin-
uous 1.544 Mb/s serial stream. There is no concept of time slot in an
unchannelized link. Each eight bits are grouped into an octet with arbi-
trary alignment. The first bit received/transmitted is the most significant
bit of an octet while the last bit is the least significant bit. The 1.544 MHz
data stream clock is provided by the system.
The 1.544 MHz clock in Tx and Rx directions can be either common
clock or independent clock. If common clock is used, TSCCK and
RSCCK are used as Tx clock and Rx clock respectively, and TSCFS and
RSCFS are used as common frame pulse in Tx and Rx directions
respectively. If independent clock is used, TSCK[i] and RSCK[i] are used
as Tx clock and Rx clock respectively, and TSF[i] and RSF[i] are used as
the frame pulse in Tx and Rx directions respectively.
3.2.1.2 Mode1~Mode4
In these four modes, the transmit/receive data rate is T1 channelized
while the line interface timing clock is 2.048 MHz (E1 clock). Thus the
mapping between T1 frame and E1 frame is needed. Two mapping
modes can be used: G.802 mapping mode and spaced mapping mode.
Each mapping mode can be further divided into two data modes: T1
ISDN mode and T1 normal mode. The mapping is done in a frame-by-
frame fashion and the unassigned time slots are set to zero.
In these modes, the clock for Tx and Rx can be either common clock
or independent clock. If common clock is used, TSCCK and RSCCK are
used as Tx clock and Rx clock respectively, and TSCFS and RSCFS are
used as common frame pulse in Tx and Rx directions respectively. If
independent clock is used, TSCK[i] and RSCK[i] are used as Tx clock
and Rx clock respectively, and TSF[i] and RSF[i] are used as the frame
pulse in Tx and Rx directions respectively.
G.802 Mapping
This mode supports ITU-T Recommendation G.802, which describes
how 24 (or 23, in signalling mode) T1 time slots and one framing bit
(totally 193/185 bits per T1/T1-ISDN frame) are mapped to 32 E1 time
slots (256 bits). This mapping is done by mapping the 24 (or 23 in T1-
ISDN mode) T1 time slots to TS1~TS15 and TS17~TS25 (or
TS17~TS24), and mapping the framing bit to bit 1 of TS26/TS25. TS0,
TS16, TS27/TS26 through TS31 are all unassigned and set to zero
(refer to Figure-5).
Table-2 Data Rates of Different Modes
Mode
IMA Data Rate Per Channel (Maximum)
Interface Clock (Maximum)
Mode0
1.544 Mb/s
1.544 MHz
Mode1
1.472 Mb/s
2.048 MHz
Mode2
1.536 Mb/s
2.048 MHz
Mode3
1.472 Mb/s
2.048 MHz
Mode4
1.536 Mb/s
2.048 MHz
Mode5
1.472 Mb/s
1.544 MHz
Mode6
1.536 Mb/s
1.544 MHz
Mode7
1.472 Mb/s
8.192 MHz
Mode8
1.536 Mb/s
8.192 MHz
Mode9
1.472 Mb/s
8.192 MHz
Mode10
1.536 Mb/s
8.192 MHz
Mode11
2.048 Mb/s
2.048 MHz
Mode12
1.920 Mb/s
2.048 MHz
Mode13
1.984 Mb/s
2.048 MHz
Mode14
1.920 Mb/s
8.192 MHz
Mode15
1.984 Mb/s
8.192 MHz
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