參數(shù)資料
型號(hào)： IDT82V2088BB
廠(chǎng)商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 18/78頁(yè)
文件大?。?/td> 0K
描述： IC LIU T1/J1/E1 8CH 208-BGA
標(biāo)準(zhǔn)包裝： 10
類(lèi)型： 線(xiàn)路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 208-BGA
供應(yīng)商設(shè)備封裝： 208-PBGA（17x17）
包裝： 托盤(pán)
其它名稱(chēng)： 82V2088BB
25
INDUSTRIAL
TEMPERATURE RANGES
OCTAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
3.4
JITTER ATTENUATOR
ThereisoneJitterAttenuatorineachchanneloftheLIU.TheJitterAtten-
uator can be deployed in the transmit path or the receive path, and can also
be disabled. This is selected by the JACF[1:0] bits (JACF, 01H...).
3.4.1
JITTER ATTENUATION FUNCTION DESCRIPTION
The Jitter Attenuator is composed of a FIFO and a DPLL, as shown in
Figure-13. The FIFO is used as a pool to buffer the jittered input data, then
the data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the JADP[1:0] bits
(JACF, 01H...). Consequently, the constant delay of the Jitter Attenuator
will be 16 bits, 32 bits or 64 bits. Deeper FIFO can tolerate larger jitter, but
at the expense of increasing data latency time.
Figure-13 Jitter Attenuator
In E1 applications, the Corner Frequency of the DPLL can be 0.9 Hz or
6.8 Hz, as selected by the JABW bit (JACF, 01H...). In T1/J1 applications,
the Corner Frequency of the DPLL can be 1.25 Hz or 5.00 Hz, as selected
by the JABW bit (JACF, 01H...). The lower the Corner Frequency is, the
longer time is needed to achieve synchronization.
When the incoming data moves faster than the outgoing data, the FIFO
will overflow. This overflow is captured by the JAOV_IS bit (INTS1, 17H...).
If the incoming data moves slower than the outgoing data, the FIFO will
underflow. This underflow is captured by the JAUD_IS bit (INTS1, 17H...).
For some applications that are sensitive to data corruption, the JA limit
mode can be enabled by setting JA_LIMIT bit (JACF, 01H...) to ‘1’. In the
JA limit mode, the speed of the outgoing data will be adjusted automatically
when the FIFO is close to its full or emptiness. The criteria of starting speed
adjustment are shown in Table-16. The JA limit mode can reduce the pos-
sibility of FIFO overflow and underflow, but the quality of jitter attenuation
is deteriorated.
3.4.2
JITTER ATTENUATOR PERFORMANCE
The performance of the Jitter Attenuator in the IDT82V2088 meets the
ITU-T I.431, G.703, G.736-739, G.823, G.824, ETSI 300011, ETSI TBR12/
13, AT&T TR62411 specifications. Details of the Jitter Attenuator perfor-
FIFO
32/64/128
DPLL
Jittered Data
De-jittered Data
Jittered Clock
De-jittered Clock
MCLK
W
R
RCLKn
RDn/RDPn
RDNn
Table-16 Criteria of Starting Speed Adjustment
FIFO Depth
Criteria for Adjusting Data Outgoing Speed
32 Bits
2 bits close to its full or emptiness
64 Bits
3 bits close to its full or emptiness
128 Bits
4 bits close to its full or emptiness
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IDT82V2088DRG 功能描述:IC LIU T1/J1/E1 8CH 208-TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
IDT82V2108 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:T1 / E1 / J1 OCTAL FRAMER
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