參數(shù)資料
型號: IDT82V2084PFG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 3/75頁
文件大小: 0K
描述: IC LIU T1/J1/E1 4CH 128-TQFP
標(biāo)準(zhǔn)包裝: 15
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 托盤
其它名稱: 82V2084PFG
11
INDUSTRIAL
TEMPERATURE RANGES
QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INT/MOT
Input
6
INT/MOT: Intel or Motorola Microcontroller Interface Select
In microcontroller mode, the parallel microcontroller interface is configured for Motorola compatible microcontrollers when this
pin is low, or for Intel compatible microcontrollers when this pin is high.
CS
Input
32
CS: Chip Select
In microcontroller mode, this pin is asserted low by the microcontroller to enable microcontroller interface. For each read or write
operation, this pin must be changed from high to low, and will remain low until the operation is over.
SCLK
Input
33
SCLK: Shift Clock
In serial microcontroller mode, signal on this pin is the shift clock for the serial interface. Configuration data on pin SDI is sampled
on the rising edges of SCLK. Configuration and status data on pin SDO is clocked out of the device on the rising edges of SCLK
if pin SCLKE is low, or on the falling edges of SCLK if pin SCLKE is high.
DS/RD
Input
34
DS: Data Strobe
In parallel Motorola microcontroller interface mode, signal on this pin is the data strobe of the parallel interface. During a write
operation (R/W =0), data on D[7:0] is sampled into the device. During a read operation (R/W =1), data is output to D[7:0] from
the device.
RD: Read Operation
In parallel Intel microcontroller interface mode, this pin is asserted low by the microcontroller to initiate a read cycle. Data is out-
put to D[7:0] from the device during a read operation.
SDI/R/W/WR
Input
35
SDI: Serial Data Input
In serial microcontroller mode, data is input on this pin. Input data is sampled on the rising edges of SCLK.
R/W: Read/Write Select
In parallel Motorola microcontroller interface mode, this pin is low for write operation and high for read operation.
WR: Write Operation
In parallel Intel microcontroller interface mode, this pin is asserted low by the microcontroller to initiate a write cycle. Data on
D[7:0] is sampled into the device during a write operation.
SDO
Output
36
SDO: Serial Data Output
In serial microcontroller mode, signal on this pin is the output data of the serial interface. Configuration and status data on pin
SDO is clocked out of the device on the active edge of SCLK.
INT
Output
37
INT: Interrupt Request
This pin outputs the general interrupt request for all interrupt sources. If INTM_GLB bit (GCF0, 40H) is set to ‘1’ all the interrupt
sources will be masked. And these interrupt sources also can be masked individually via registers (INTM0, 11H) and (INTM1,
12H). Interrupt status is reported via byte INT_CH (INTCH, 80H), registers (INTS0, 16H) and (INTS1, 17H).
Output characteristics of this pin can be defined to be push-pull (active high or low) or be open-drain (active low) by bits
INT_PIN[1:0] (GCF0, 40H).
D7
D6
D5
D4
D3
D2
D1
D0
I / O
Tri-state
14
15
16
17
18
19
20
21
Dn: Data Bus 7~0
These pins function as a bi-directional data bus of the microcontroller interface.
A7
A6
A5
A4
A3
A2
A1
A0
Input
24
25
26
27
28
29
30
31
An: Address Bus 7~0
These pins function as an address bus of the microcontroller interface.
RST
Input
38
RST: Hardware Reset
The chip is reset if a low signal is applied on this pin for more than 100ns. All the drivers output are in high-impedance state,
all the internal flip-flops are reset and all the registers are initialized to their default values.
Table-1 Pin Description (Continued)
Name
Type
TQFP128
Description
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